參數(shù)資料
型號(hào)： FW82439TX
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 61/102頁(yè)
文件大?。?/td> 759K
代理商： FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
61
PRELIMINARY
4.3.6.
AUTO DETECTION
The SDRAM, FPM, and EDO detection is performed by BIOS. Note that when accessing any of the DRAM
related registers (i.e., 54h–68h), refresh should be turned off via the DRAM Control register (DRAMC).
4.3.7.
DRAM PERFORMANCE
The DRAM performance is controlled by the DRAM timing register, processor pipelining, and by the type of
DRAM used (EDO or FPM or SDRAM). Table 17 depicts both EDO and standard page mode optimum
timings. For read cycles, clocks counts are measured from ADS# to BRDY#.
For write cycles, the measurement is broken up into two parts. The first part consists of the rate of posting
data in to the CPU to DRAM posted write buffers. This is measured from ADS# to BRDY#. The second part
consists of the retire rate from posted write buffers to the DRAM. The leadoff for retiring is measured from the
clock after BRDY# assertion to the CAS# assertion.
Table 17 lists the performance summary for 60 ns EDO/FPM DRAMs. The four row column is assuming each
row is populated with a maximum of 16, x4 devices=64 DRAM devices. The five row column is assuming
each of the first four rows is populated with a maximum of 16, x4 devices and the fifth row is populated with a
maximum of eight, x8 devices=72 DRAM devices. The six row column assumes that each of the six rows can
be populated with a maximum of 16, x4 devices.
The FELO and SLD bits are used to control the leadoff for read cycles (page hit, row miss, and page miss).
Each bit removes one clock from the leadoff, when enabled. Note that FELO impacts EDO only and must be
disabled for FPM. The DLT bits are used to control the base starting point for the leadoff for read/write cycles
(page miss and row miss, only).
相關(guān)PDF資料
PDF描述
FW82815 Controller Miscellaneous - Datasheet Reference
FWA-25A10F Fuse
FWA-30A10F Fuse
FWA-35A21F Fuse
FWA-40A21F Fuse
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參數(shù)描述
FW82439TX S L28T 制造商:Intel 功能描述:System Controller 324-Pin BGA
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