參數(shù)資料
型號: FW82439TX
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 33/102頁
文件大?。?/td> 759K
代理商: FW82439TX
Extended Temperature 82439TX (MTXC) Datasheet
33
PRELIMINARY
Bit
Description
1
64-Mbit Technology Enable (64MTEN).
1=Enable. 0=Disable. When set to 0, the MTXC does
not support 64-Mbit SDRAM devices. In this mode, the MTXC supports 4-Mbit, 16-Mbit, and 64-
Mbit technology for EDO/FPM systems and 4 Mbit and 16 Mbit for SDRAM systems (i.e., 64 Mbit
not supported in SDRAM systems). When set to 1, the MTXC supports 4 Mbit, 16 Mbit, and 64
Mbit for both SDRAM and EDO/FPM devices. In this mode, the RAS5#/CS5# signal becomes
RAS5#/CS5#/MA13, RAS4#/CS4# becomes RAS4#/CS4#/BA1, and KRQAK/CS4_64# becomes
CS4_64#. CS4_64# (fifth row) function is provided if this signal is set to 1 and DRAM Cache is
not present in the system (indicated by a 0 in bit 5, register 53h).
0
Reserved.
Table 4 lists the CAS# Latency, RAS# to CAS#, RAS# Precharge, RAS# Active to Precharge and Refresh to
RAS# active programmable timings.
Table 4. Programming Timings
Operating
Frequency
CAS
Latency (CL)
RAS# to
CAS# (Trcd)
RAS#
Precharge
(Trp)
RAS# active
to Precharge
(Tras)
Refresh to
RAS# (Trc)
Register 54h
Bits[5:3]
60/66 MHz
3 HCLKs
3 HCLKs
3 HCLKs
5 HCLKs
8 HCLKs
000
60/66 MHz
3 HCLKs
2 HCLKs
3 HCLKs
5 HCLKs
8 HCLKs
100
60/66 MHz
2 HCLKs
2 HCLKs
3 HCLKs
4 HCLKs
7 HCLKs
011
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