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參數(shù)資料
| 型號： | FW82439TX |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 28/102頁 |
| 文件大?。?/td> | 759K |
| 代理商： | FW82439TX |
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Extended Temperature 82439TX (MTXC) Datasheet
28
PRELIMINARY
3.1.11.
HEDT
HEADER TYPE REGISTER
Address Offset:
Default Value:
Access:
0Eh
00h
Read Only
This register contains the Header Type of the MTXC. This code is 00h indicating that the MTXC’s
configuration space map follows the basic format.
Bit
Description
7:0
Device Type (DEVICET).
00h=Indicates a basic configuration space format.
3.1.12.
BIST
BIST REGISTER
Address Offset:
Default Value:
Access:
0Fh
00h
Read/Write
The Built In Self Test (BIST) function is not supported by the MTXC. Writes to this register have no effect.
Bit
Description
7
BIST Supported
.
This read only bit is always set to 0, disabling the BIST function. Writes to this
bit position have no effect.
Start BIST
.
This function is not supported and writes have no effect.
Reserved
.
Completion Code
.
This read only field always returns 0 when read and writes have no effect.
6
5:4
3:0
3.1.13.
ACON
ARBITRATION CONTROL REGISTER
Address Offset:
Default Value:
Access:
4Fh
00h
Read/Write
The ACON Register enables and disables features related to PCI arbitration and PCI 2.1 compliance.
Bit
Description
7
Extended CPU-to-PIIX4 PHLDA# Signaling Enable (XPLDE).
When XPLDE=1,
the MTXC adds
the following additional signaling to signal PHLDA# (i.e., in addition to the normal CPU/PIIX4
PHOLD/PHLDA# protocol):
1. Whenever the North bridge begins a PCI read/write transaction, it will assert PHLDA# for
1 PCLK within the address phase of the transaction.
2. If the CPU is attempting a LOCKed cycle AND LOCK has been established (i.e. PLOCK# was
seen negated in address phase), the PHLDA# remains asserted for one additional clock
following the address phase.
This bit should be set to 1 anytime both Passive Release and Delayed Transaction are enabled in
the PIIX4. Passive release and delayed transaction are enabled via bits 1 and 0 in PIIX4 register
82h (function 0). When bit 7 in this register is set to 1 (enabled), Bit 7 in PIIX4 Register, 6A
(Function 0) must also be set to 1. When enabling these two bits, enable Bit 7 in the PIIX4 first,
followed by bit 7 in this register. When disabling these two bits, disable Bit 7 in this register first,
followed by bit 7 in the PIIX4.
6:0
Reserved.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FW82815 | Controller Miscellaneous - Datasheet Reference |
| FWA-25A10F | Fuse |
| FWA-30A10F | Fuse |
| FWA-35A21F | Fuse |
| FWA-40A21F | Fuse |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FW82439TX S L28T | 制造商:Intel 功能描述:System Controller 324-Pin BGA |
| FW82439TX S L3BT | 制造商:Intel 功能描述:System Controller |
| FW82439TX S L28T | 制造商:Intel 功能描述: |
| FW82439TX S L3BT | 制造商:Intel 功能描述:System Controller |
| FW82439TXSL28T | 功能描述:IC 82439TX SYS CTRL MTXC 324BGA RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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