- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380224 > CYRF69103 (Cypress Semiconductor Corp.) Programmable Radio on Chip Low Power PDF資料下載
參數(shù)資料
| 型號： | CYRF69103 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | 可編程片上無線電低功耗 |
| 文件頁數(shù)： | 55/73頁 |
| 文件大?。?/td> | 683K |
| 代理商： | CYRF69103 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁當(dāng)前第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁
CYRF69103
Document #: 001-07611 Rev *B
Page 55 of 73
Mnemonic
XACT_CFG_ADR
Address
0x0F
Bit
7
6
5
4
3
2
1
0
Default
1
-
0
0
0
0
0
0
Read/Write
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
Function
ACK EN
Not Used
FRC END
END STATE
ACK TO
Bit 7
Acknowledge Enable. When this bit is set, an ACK packet is automatically transmitted whenever a valid packet is received; in
this case the device is considered to be in transaction mode. After transmission of the ACK packet, the device automatically
transitions to the END STATE. When this bit is cleared, the device transitions directly to the END STATE immediately after the
end of packet transmission.
Force End State. Setting this bit forces a transition to the state set in END STATE. By setting the desired END STATE at the
same time as setting this bit the device may be forced to immediately transition from its current state to any other state. This bit
is automatically cleared upon completion.
Transaction End State. This field defines the mode to which the device transitions after receiving or transmitting a packet. 000 =
Sleep Mode, 001 = Idle Mode, 010 = Synth Mode (TX), 011 = Synth Mode (RX), 100 = RX Mode. In normal use, this field will
typically be set to 000 or 001 when the device is transmitting packets, and 100 when the device is receiving packets. Note that
when the device transitions to receive mode as an END STATE, the receiver must still be armed by setting RX GO before the
device can begin receiving data. If the system only support packets <=16 bytes then firmware should examine RXC IRQ and
RXE IRQ to determine the status of the packet. If the system supports packets > 16 bytes ensure that END STATE is not sleep,
force RXF = 1, perform receive operation, force RXF = 0, and if necessary set END STATE back to sleep.
ACK Timeout. When the device is configured for transaction mode, this field sets the timeout period after transmission of a
packet during which an ACK must be correctly received in order to prevent a transmit error condition from being detected. This
timeout period is expressed in terms of a number of SOP_CODE_ADR code lengths; if SOP LEN is set, then the timeout period
is this value multiplied by 64
μ
s and if SOP LEN is cleared then the timeout is this value multiplied by 32
μ
s. 00 = 4x, 01 = 8x,
10 = 12x, 11 = 15x the SOP_CODE_ADR code length. ACK_TO must be set to greater than 30 + Data Code Length (only for
8DR) + Preamble Length + SOP Code Length (x2).
Bit 5
Bits 4:2
Bits 1:0
Mnemonic
FRAMING_CFG_ADR
Address
0x10
Bit
7
6
5
4
3
2
1
0
Default
1
0
1
0
0
1
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
SOP EN
SOP LEN
LEN EN
SOP TH
Bit 7
SOP Enable. When this bit is set, each transmitted packet begins with a SOP field, and only packets beginning with a valid
SOP field will be received. If this bit is cleared, no SOP field will be generated when a packet is transmitted, and packet recep-
tion will begin whenever two successive correlations against the DATA_CODE_ADR code are detected.
SOP PN Code Length. When this bit is set the SOP_CODE_ADR code length is 64 chips. When this bit is cleared the
SOP_CODE_ADR code length is 32 chips.
Packet Length Enable. When this bit is set the 8-bit value contained in TX_LENGTH_ADR is transmitted immediately after the
SOP field. In receive mode, the 8 bits immediately following the SOP field are interpreted as the length of the packet. When this
bit is cleared no packet length field is transmitted. 8DR always sends the packet length field (forces LEN EN = 1). GFSK
requires user set LEN EN = 1.
SOP Correlator Threshold. This is the receive data correlator threshold used when attempting to detect a SOP symbol. There
is a threshold for the SOP_CODE_ADR code. This (single) threshold is applied independently to each of SOP1 and SOP2
fields. There are then two thresholds for each of the 64-chip DATA_CODE_ADR codes and 32 chip DATA_CODE_ADR codes.
When SOP LEN is set, all 5 bits of this field are used. When SOP LEN is cleared, the most significant bit is disregarded. Typical
applications configure SOP TH = 04h for SOP32 and SOP TH = 0Eh for SOP64.
Bit 6
Bit 5
Bits 4:0
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYRF69213 | Programmable Radio on Chip Low Power |
| CYRF69213-40LFXC | Programmable Radio on Chip Low Power |
| CYRF6936-40LFXC | WirelessUSB⑩ LP 2.4 GHz Radio SoC |
| CYS25G0101DX-ATC | SONET OC-48 Transceiver |
| CYS25G0101DX-ATI | SONET OC-48 Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYRF69103_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power |
| CYRF69103_10 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power |
| CYRF69103_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power 16-bit free running timer |
| CYRF69103_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power |
| CYRF69103_13 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。