
CYRF69103
Document #: 001-07611 Rev *B
Page 53 of 73
Mnemonic
PWR_CTRL_ADR
Address
1
0x0B
Bit
7
6
5
4
3
2
0
Default
1
0
1
-
0
0
0
0
Read/Write
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
Function
PMU EN
LVIRQ EN
PMU Mode
Force
Not Used
LVI TH
PMU OUTV
Bit 7
Power Management Unit (PMU) Enable. Setting this bit enables the PMU if PMU Mode Force bit (bit-5) is set, otherwise it has
no effect. See PMU Mode Force bit description.
Low Voltage Interrupt Enable. Setting this bit enables the LV IRQ interrupt. When this interrupt is enabled, if the V
BAT
voltage
falls below the threshold set by LVI TH, then a low voltage interrupt will be generated. The LVI is not available when the device
is in sleep mode. The LVI event on IRQ pin is automatically disabled whenever the PMU is disabled.
PMU Mode Force. If this bit is set the PMU operation will be based on the value of the PMU EN bit (bit 7). If this bit is not set the
PMU is disabled during sleep. Otherwise it is enabled when not in Sleep mode.
Low Voltage Interrupt Threshold. This field sets the voltage on V
BAT
at which the LVI is triggered. 11 = 1.8V, 10 = 2.0V,
01 = 2.2V, 00 = PMU OUTV voltage.
PMU Output Voltage. This field sets the minimum output voltage of the PMU. 11 = 2.4V, 10 = 2.5V, 01 = 2.6V, 00 = 2.7V. When
the PMU is active, the voltage output by the PMU on V
REG
will never be less than this voltage provided that the total load on the
V
REG
pin is less than the specified maximum value, and the voltage in V
BAT
is greater than the specified minimum value.
To force the chip to always enable the PMU (even during sleep), set bits 5 and 7. To force the chip to always disable the PMU, set bit 5 and
clear bit 7. To allow the chip to disable the PMU during sleep, clear bit 5.
The sequence of writing bits to this register impacts the sleep current I
SB
.
Bit 6
Bit 5
Bits 3:2
Bits 1:0
Mnemonic
XTAL_CTRL_ADR
Address
1
0x0C
Bit
7
6
5
4
3
2
0
Default
0
0
0
-
-
1
0
0
Read/Write
R/W
R/W
R/W
-
-
R/W
R/W
R/W
Function
XOUT FN
XSIRQ EN
Not Used
Not Used
FREQ
Bits 7:6
XOUT Pin Function. This field selects between the different functions of the XOUT pin. 00 = Clock frequency set by XOUT
FREQ; 01 = Active LOW PA Control; 10 = Radio data serial bit stream. If this option is selected and SPI is configured for 3-wire
mode then the MISO pin will output a serial clock associated with this data stream; 11 = GPIO. To disable this output, set to
GPIO mode, and set the GPIO state in IO_CFG_ADR.
Crystal Stable Interrupt Enable. This bit enables the OS IRQ interrupt. When enabled, this interrupt generates an IRQ event
when the crystal has stabilized after the device has woken from sleep mode. This event is cleared by writing zero to this bit.
XOUT Frequency. This field sets the frequency output on the XOUT pin when XOUT FN is set to 00. 0 = 12 MHz, 1 = 6 MHz,
2 = 3 MHz, 3 = 1.5 MHz, 4 = 0.75 MHz; other values are not defined.
Bit 5
Bits 2:0
[+] Feedback