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| 型號： | CYRF69103 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | 可編程片上無線電低功耗 |
| 文件頁數(shù)： | 43/73頁 |
| 文件大小： | 683K |
| 代理商： | CYRF69103 |
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CYRF69103
Document #: 001-07611 Rev *B
Page 43 of 73
Interrupt Mask Registers
The Interrupt Mask Registers (INT_MSKx) are used to enable
the individual interrupt sources’ ability to create pending inter-
rupts.
There are four Interrupt Mask Registers (INT_MSK0,
INT_MSK1, INT_MSK2, and INT_MSK3), which may be
referred to in general as INT_MSKx. If cleared, each bit in an
INT_MSKx register prevents a posted interrupt from becoming
a pending interrupt (input to the priority encoder). However, an
interrupt can still post even if its mask bit is zero. All INT_MSKx
bits are independent of all other INT_MSKx bits.
If an INT_MSKx bit is set, the interrupt source associated with
that mask bit may generate an interrupt that will become a
pending interrupt.
The Enable Software Interrupt (ENSWINT) bit in INT_MSK3[7]
determines the way an individual bit value written to an
INT_CLRx register is interpreted. When is cleared, writing 1's
to an INT_CLRx register has no effect. However, writing 0's to
an INT_CLRx register, when ENSWINT is cleared, will cause
the corresponding interrupt to clear. If the ENSWINT bit is set,
any 0's written to the INT_CLRx registers are ignored.
However, 1's written to an INT_CLRx register, while ENSWINT
is set, will cause an interrupt to post for the corresponding
interrupt.
Software interrupts can aid in debugging interrupt service
routines by eliminating the need to create system level inter-
actions that are sometimes necessary to create a
hardware-only interrupt.
Table 66. Interrupt Clear 1 (INT_CLR1) [0xDB] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Read/Write
Default
When reading this register,
0 = There’s no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits will clear the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT
Bit 7
Reserved
Reserved
Prog Interval
Timer
1-ms Pro-
grammable In-
terrupt
R/W
0
Reserved
-
0
R/W
0
–
0
–
0
–
0
–
0
–
0
Table 67.Interrupt Clear 2 (INT_CLR2) [0xDC] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Read/Write
Default
When reading this register,
0 = There’s no posted interrupt for the corresponding hardware
1 = Posted interrupt for the corresponding hardware present
Writing a ‘0’ to the bits will clear the posted interrupts for the corresponding hardware. Writing a ‘1’ to the bits AND to the ENSWINT (Bit 7 of the
INT_MSK3 Register) will post the corresponding hardware interrupt
Bits 7,6,5,3,0] Reserved
Reserved
Reserved
Reserved
GPIO Port2
Reserved
INT2
16-bit Counter
Wrap
R/W
0
Reserved
–
0
-
0
-
0
R/W
0
–
0
R/W
0
-
0
Table 68.Interrupt Mask 3 (INT_MSK3) [0xDE] [R/W]
Bit #
Field
Read/Write
Default
Bit 7
7
6
5
4
3
2
1
0
ENSWINT
R
0
Enable Software Interrupt (ENSWINT)
0 = Disable. Writing 0's to an INT_CLRx register, when ENSWINT is cleared, will cause the corresponding interrupt to clear
1 = Enable. Writing 1's to an INT_CLRx register, when ENSWINT is set, will cause the corresponding interrupt to post
Reserved
Reserved
–
0
–
0
–
0
–
0
–
0
–
0
–
0
Bits 6:0
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