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參數(shù)資料
| 型號(hào)： | CYRF69103 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | 可編程片上無線電低功耗 |
| 文件頁數(shù)： | 32/73頁 |
| 文件大?。?/td> | 683K |
| 代理商： | CYRF69103 |
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CYRF69103
Document #: 001-07611 Rev *B
Page 32 of 73
Table 45.P0.1/CLKOUT Configuration (P01CR) [0x06] R/W]
Bit #
Field
Read/Write
Default
This pin is shared between P0.1 GPIO use and the CLKOUT pin for the external crystal oscillator. When the external oscillator is enabled the
settings of this register are ignored. When CLK output is set, the internally selected clock is sent out onto P0.1CLKOUT pin
The alternate function of the pin as the CLKOUT is only available in the CY7C601xx. When the external oscillator is enabled (the XOSC Enable
bit of the CLKIOCR Register is set—
Table 73
), the GPIO function of the pin is disabled
The 50-mA sink drive capability is only available in the CY7C601xx. In the CY7C602xx, only 8-mA sink drive capability is available on this pin
regardless of the setting of the High Sink bit
If this pin is used as a general-purpose output it will draw current. This pin should be configured as an input to reduce current draw
Bit 7
CLK Output
0 = The clock output is disabled
1 = The clock selected by the CLK Select field (Bit [1:0] of the CLKIOCR Register—
Table 73
) is driven out to the pin
7
6
5
4
3
2
1
0
CLK Output
R/W
0
Int Enable
R/W
0
Int Act Low
R/W
0
TTL Thresh
R/W
0
High Sink
R/W
0
Open Drain
R/W
0
Pull-up Enable Output Enable
R/W
0
R/W
0
Table 46.P0.3–P0.4 Configuration (P03CR–P04CR) [0x07–0x09] [R/W]
Bit #
Field
Read/Write
Default
These registers control the operation of pins P0.2–P0.4 respectively. These pins are shared between the P0.2–P0.4 GPIOs and the INT0–INT2.
The INT0–INT2 interrupts are different than all the other GPIO interrupts. These pins are connected directly to the interrupt controller to provide
three edge-sensitive interrupts with independent interrupt vectors. These interrupts occur on a rising edge when Int act Low is clear and on a
falling edge when Int act Low is set. These pins are enabled as interrupt sources in the interrupt controller registers (
Table 71
and
Table 69
)
To use these pins as interrupt inputs, configure them as inputs by clearing the corresponding Output Enable. If the INT0–INT2 pins are configured
as outputs with interrupts enabled, firmware can generate an interrupt by writing the appropriate value to the P0.2, P0.3, and P0.4 data bits in
the P0 Data Register
Regardless of whether the pins are used as Interrupt or GPIO pins the Int Enable, Int act Low, TTL Threshold, Open Drain, and Pull-up Enable
bits control the behavior of the pin
The P0.2/INT0–P0.4/INT2 pins are individually configured with the P02CR (0x07), P03CR (0x08), and P04CR (0x09) respectively
Note
Changing the state of the Int Act Low bit can cause an unintentional interrupt to be generated. When configuring these interrupt sources,
it is best to follow the following procedure:
1. Disable interrupt source
2. Configure interrupt source
3. Clear any pending interrupts from the source
4. Enable interrupt source
7
6
5
4
3
2
1
0
Reserved
Int Act Low
R/W
0
TTL Thresh
R/W
0
Reserved
–
0
Open Drain
R/W
0
Pull-up Enable Output Enable
R/W
0
–
0
–
0
R/W
0
Table 47.P0.7 Configuration (P07CR) [0x0C] [R/W]
Bit #
Field
Read/Write
Default
This register controls the operation of pin P0.7
7
6
5
4
3
2
1
0
Reserved
–
0
Int Enable
R/W
0
Int Act Low
R/W
0
TTL Thresh
R/W
0
Reserved
–
0
Open Drain
R/W
0
Pull-up Enable Output Enable
R/W
0
R/W
0
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