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參數(shù)資料
| 型號： | CYRF69103 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | 可編程片上無線電低功耗 |
| 文件頁數(shù)： | 20/73頁 |
| 文件大小： | 683K |
| 代理商： | CYRF69103 |
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CYRF69103
Document #: 001-07611 Rev *B
Page 20 of 73
Firmware is responsible for selecting the correct trim values
from the User row to match the power supply voltage in the
end application and writing the values to the trim registers
IOSCTR and LPOSCTR.
The internal low-speed oscillator of nominally 32 KHz provides
a slow clock source for the CYRF69103 in suspend mode,
particularly to generate a periodic wake-up interrupt and also
to provide a clock to sequential logic during power-up and
power-down events when the main clock is stopped. In
addition, this oscillator can also be used as a clocking source
for the Interval Timer clock (ITMRCLK) and Capture Timer
clock (TCAPCLK). The 32-kHz Low-power Oscillator can
operate in low-power mode or can provide a more accurate
clock in normal mode. The Internal 32-kHz Low-power Oscil-
lator accuracy ranges from –53.12% to +56.25%. The 32-KHz
low power oscillator can be calibrated against the internal
24-MHz oscillator or another timing source if desired.
CYRF69103 provides the ability to load new trim values for the
24-MHz oscillator based on voltage. This allows Vdd to be
monitored and have firmware trim the oscillator based on
voltage present. The IOSCTR register is used to set trim
values for the 24-MHz oscillator. CYRF69103 is initialized with
3.30V trim values at power-on, then firmware is responsible for
transferring the correct set of trim values to the trim registers
to match the application’s actual Vdd. The 32-KHz oscillator
generally does not require trim adjustments vs. voltage but
trim values for the 32-KHz are also stored in Supervisory
ROM.
When using the 32-KHz oscillator the PITMRL/H should be
read until two consecutive readings match before
sending/receiving data. The following firmware example
assumes the developer is interested in the lower byte of the
PIT.
Read_PIT_counter:
mov A, reg[PITMRL]
mov [57h], A
mov A, reg[PITMRL]
mov [58h],A
mov [59h], A
mov A, reg[PITMRL]
mov [60h], A
;;;Start comparison
mov A,[60h]
mov X, [59h]
sub A, [59h]
jz done
mov A, [59h]
mov X, [58h]
sub A, [58h]
jz done
mov X, [57h]
;;;correct data is in memory location 57h
done:
mov [57h], X
ret
The CYRF69103 can optionally be sourced from an external
crystal oscillator. The external clock driving on CLKIN range is
from 187 KHz to 24 MHz.
Clock Architecture Description
The CYRF69103 clock selection circuitry allows the selection
of independent clocks for the CPU, Interval Timers, and
Capture Timers.
On the CYRF69103, the external oscillator can be sourced by
the crystal oscillator, or when the crystal oscillator is disabled
it is sourced directly from the CLKIN pin.
CPU Clock
The CPU clock, CPUCLK, can be sourced from the external
crystal oscillator, the Internal 24-MHz Oscillator, or the Internal
32-KHz Low-power Oscillator. The selected clock source can
optionally be divided by 2
n-1
where
n
is 0–7 (see
Table 33
).
Table 31. Oscillator Trim Values vs. Voltage Settings
Supervisory FLASH
User Row Address
0xC094
0xC095
0xC096
0xC097
0xC098
0xC099
0xC09A
0xC09B
Function
24-MHz IOSCTR @ 3.30V
24-MHz IOSCTR @ 3.00V
24-MHz IOSCTR @ 2.85V
24-MHz IOSCTR @ 2.70V
32-kHz LPOSCTR@3.30V
32-kHz LPOSCTR@3.00V
32-kHz LPOSCTR@2.85V
32-kHz LPOSCTR@2.70V
Table 32.CPU Clock Config (CPUCLKCR) [0x30] [R/W]
Bit #
Field
Read/Write
Default
Bits 7:1
Bit 0
7
6
5
4
3
2
1
0
Reserved
–
0
Reserved
-
0
–
0
–
0
–
0
–
0
–
0
–
0
Reserved
CPU CLK Select
0 = Internal 24-MHz Oscillator
1 = Reserved to 0
Note
The CPU speed selection is configured using the OSC_CR0 Register (
Figure 11
)
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