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參數(shù)資料
| 型號： | CYRF69103 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | 可編程片上無線電低功耗 |
| 文件頁數(shù)： | 45/73頁 |
| 文件大小： | 683K |
| 代理商： | CYRF69103 |
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CYRF69103
Document #: 001-07611 Rev *B
Page 45 of 73
Interrupt Vector Clear Register
Table 71. Interrupt Mask 0 (INT_MSK0) [0xE0] [R/W]
Bit #
7
6
5
4
3
2
1
0
Field
Read/Write
Default
Bit 7
GPIO Port 1
Int Enable
R/W
0
GPIO Port 1 Interrupt Enable
0 = Mask GPIO Port 1 interrupt
1 = Unmask GPIO Port 1 interrupt
Sleep Timer Interrupt Enable
0 = Mask Sleep Timer interrupt
1 = Unmask Sleep Timer interrupt
INT1 Interrupt Enable
0 = Mask INT1 interrupt
1 = Unmask INT1 interrupt
GPIO Port 0 Interrupt Enable
0 = Mask GPIO Port 0 interrupt
1 = Unmask GPIO Port 0 interrupt
SPI Receive Interrupt Enable
0 = Mask SPI Receive interrupt
1 = Unmask SPI Receive interrupt
SPI Transmit Enable
0 = Mask SPI Transmit interrupt
1 = Unmask SPI Transmit interrupt
Reserved
POR/LVD Interrupt Enable
0 = Mask POR/LVD interrupt
1 = Unmask POR/LVD interrupt
Sleep Timer
Int Enable
R/W
0
INT1
Int Enable
R/W
0
GPIO Port 0
Int Enable
R/W
0
SPI Receive
Int Enable
R/W
0
SPI Transmit
Int Enable
R/W
0
Reserved
POR/LVD
Int Enable
R/W
0
R/W
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Table 72.Interrupt Vector Clear Register (INT_VC) [0xE2] [R/W]
Bit #
Field
Read/Write
Default
The Interrupt Vector Clear Register (INT_VC) holds the interrupt vector for the highest priority pending interrupt when read, and when written
will clear all pending interrupts
Bits 7:0
Pending Interrupt [7:0]
8-bit data value holds the interrupt vector for the highest priority pending interrupt. Writing to this register will clear all pending interrupts
7
6
5
4
3
2
1
0
Pending Interrupt [7:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Microcontroller Function Register Summary
Addr
Name
7
6
5
4
3
2
1
0
R/W
Default
00
P0DATA
P0.7
Reserved
Reserved
P0.4/INT2
P0.3/INT1
Reserved
P0.1/
CLKOUT
Reserved
b--bb-b-
00000000
01
P1DATA
P1.7
P1.6/SMISO P1.5/SMOSI
P1.4/SCLK
P1.3/SSEL
P1.2
P1.1
P1.0
bbbbbbb-
00000000
02
P2DATA
Reserved
P2.1–P2.0
------bb
00000000
06
P01CR
CLK Output
Int Enable
Int Act Low
TTL Thresh
High Sink
Open Drain
Pull-up
Enable
Output
Enable
bbbbbbbb
00000000
08–09
P03CR–
P04CR
Reserved
Int Act Low
TTL Thresh
Reserved
Open Drain
Pull-up
Enable
Output
Enable
--bb-bbb
00000000
0C
P07CR
Reserved
Int Enable
Int Act Low
TTL Thresh
Reserved
Open Drain
Pull-up
Enable
Output
Enable
-bbb-bbb
00000000
[+] Feedback
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