- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380224 > CYRF69103 (Cypress Semiconductor Corp.) Programmable Radio on Chip Low Power PDF資料下載
參數(shù)資料
| 型號： | CYRF69103 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | 可編程片上無線電低功耗 |
| 文件頁數(shù)： | 31/73頁 |
| 文件大?。?/td> | 683K |
| 代理商： | CYRF69103 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁
CYRF69103
Document #: 001-07611 Rev *B
Page 31 of 73
GPIO Port Configuration
All the GPIO configuration registers have common configu-
ration controls. The following are the bit definitions of the GPIO
configuration registers. By default all GPIOs are configured as
inputs. In order to prevent the inputs from floating, the pull-up
resistors are enabled. Firmware will need to configure each of
the GPIOs prior to use.
Int Enable
When set, the Int Enable bit allows the GPIO to generate inter-
rupts. Interrupt generate can occur regardless of whether the
pin is configured for input or output. All interrupts are edge
sensitive, however for any interrupt that is shared by multiple
sources (that is, Ports 2, 3, and 4) all inputs must be
deasserted before a new interrupt can occur.
When clear, the corresponding interrupt is disabled on the pin.
It is possible to configure GPIOs as outputs, enable the
interrupt on the pin and then to generate the interrupt by
driving the appropriate pin state. This is useful in test and may
have value in applications as well.
Int Act Low
When clear, the corresponding interrupt is active HIGH. When
set, the interrupt is active LOW. For P0.2–P0.4 Int act Low
clear causes interrupts to be active on the rising edge. Int act
Low set causes interrupts to be active on the falling edge.
TTL Thresh
When set, the input has TTL threshold. When clear, the input
has standard CMOS threshold.
Important Note
The GPIOs default to CMOS threshold.
User’s firmware needs to configure the threshold to TTL mode
if necessary.
High Sink
When set, the output can sink up to 50 mA.
When clear, the output can sink up to 8 mA.
On the CY7C601xx, only the P3.7, P2.7, P0.1, and P0.0 have
50-mA sink drive capability. Other pins have 8-mA sink drive
capability.
On the CY7C602xx, only the P1.7–P1.3 have 50-mA sink drive
capability. Other pins have 8-mA sink drive capability.
Open Drain
When set, the output on the pin is determined by the Port Data
Register. If the corresponding bit in the Port Data Register is
set, the pin is in high impedance state. If the corresponding bit
in the Port Data Register is clear, the pin is driven LOW.
When clear, the output is driven LOW or HIGH.
Pull-up Enable
When set the pin has a 7K pull up to V
DD
.
When clear, the pull up is disabled.
Output Enable
When set, the output driver of the pin is enabled.
When clear, the output driver of the pin is disabled.
For pins with shared functions there are some special cases.
P0.0 (CLKIN) and P0.1 (CLKOUT) can not be output enabled
when the crystal oscillator is enabled. Output enables for these
pins are overridden by XOSC Enable.
P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI) and P1.6 (SMISO)
can be used for their dedicated functions or for GPIO. To
enable the pin for GPIO use, clear the corresponding SPI Use
bit or the Output Enable will have no effect.
SPI Use
The P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI) and P1.6
(SMISO) pins can be used for their dedicated functions or for
GPIO. To enable the pin for GPIO, clear the corresponding SPI
Use bit. The SPI function controls the output enable for its
dedicated function pins when their GPIO enable bit is clear.
Table 44.P2 Data Register (P2DATA) [0x02] [R/W]
Bit #
Field
Read/Write
Default
This register contains the data for Port 2. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register
returns the current state of the Port 2 pins
Bits 7:2
P2 Data [7:2]
Bits 1:0
P2 Data [1:0]
7
6
5
4
3
2
1
0
Reserved
-
-
P2.1–P2.0
R/W
0
R/W
0
[+] Feedback
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYRF69213 | Programmable Radio on Chip Low Power |
| CYRF69213-40LFXC | Programmable Radio on Chip Low Power |
| CYRF6936-40LFXC | WirelessUSB⑩ LP 2.4 GHz Radio SoC |
| CYS25G0101DX-ATC | SONET OC-48 Transceiver |
| CYS25G0101DX-ATI | SONET OC-48 Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYRF69103_08 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power |
| CYRF69103_10 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power |
| CYRF69103_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power 16-bit free running timer |
| CYRF69103_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power |
| CYRF69103_13 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Programmable Radio on Chip Low Power |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。