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參數(shù)資料
| 型號： | CYRF69103 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | 可編程片上無線電低功耗 |
| 文件頁數(shù)： | 36/73頁 |
| 文件大?。?/td> | 683K |
| 代理商： | CYRF69103 |
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CYRF69103
Document #: 001-07611 Rev *B
Page 36 of 73
SPI Data Register
When an interrupt occurs to indicate to firmware that an byte of receive data is available, or the transmitter holding register is
empty, firmware has 7 SPI clocks to manage the buffers—to empty the receiver buffer, or to refill the transmit holding register.
Failure to meet this timing requirement will result in incorrect data transfer.
SPI Configure Register
Table 54.SPI Data Register (SPIDATA) [0x3C] [R/W]
Bit #
Field
Read/Write
Default
When read, this register returns the contents of the receive buffer. When written, it loads the transmit holding register.
Bits 7:0
SPI Data [7:0]
7
6
5
4
3
2
1
0
SPIData[7:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Table 55.SPI Configure Register (SPICR) [0x3D] [R/W]
Bit #
Field
Read/Write
Default
Bit 7
7
6
5
4
3
2
1
0
Swap
R/W
0
LSB First
R/W
0
Comm Mode
R/W
0
CPOL
R/W
0
CPHA
R/W
0
SCLK Select
R/W
0
R/W
0
R/W
0
Swap
0 = Swap function disabled
1 = The SPI block swaps its use of SMOSI and SMISO. Among other things, this can be useful in implementing single wire
SPI-like communications
LSB First
0 = The SPI transmits and receives the MSB (Most Significant Bit) first
1 = The SPI transmits and receives the LSB (Least Significant Bit) first
Comm Mode [1:0]
0 0: All SPI communication disabled
0 1: SPI master mode
1 0: SPI slave mode
1 1: Reserved
CPOL
This bit controls the SPI clock (SCLK) idle polarity
0 = SCLK idles low
1 = SCLK idles high
CPHA
The Clock Phase bit controls the phase of the clock on which data is sampled.
Table 56
shows the timing for the various com-
binations of LSB First, CPOL, and CPHA
SCLK Select
This field selects the speed of the master SCLK. When in master mode, SCLK is generated by dividing the base CPUCLK
Important Note for Comm Modes 01b or 10b (SPI Master or SPI Slave):
When configured for SPI, (SPI Use = 1—
Table 51
), the input/output direction of pins P1.3, P1.5, and P1.6 is set automatically by the SPI logic.
However, pin P1.4's input/output direction is NOT automatically set; it must be explicitly set by firmware. For SPI Master mode, pin P1.4 must
be configured as an output; for SPI Slave mode, pin P1.4 must be configured as an input
Bit 6
Bits 5:4
Bit 3
Bit 2
Bits 1:0
[+] Feedback
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