參數(shù)資料
型號(hào)： CYRF69103
廠商： Cypress Semiconductor Corp.
英文描述： Programmable Radio on Chip Low Power
中文描述： 可編程片上無線電低功耗
文件頁數(shù)： 50/73頁
文件大?。?/td> 683K
代理商： CYRF69103
CYRF69103
Document #: 001-07611 Rev *B
Page 50 of 73
Mnemonic
RX_CTRL_ADR
Address
1
0x05
Bit
7
6
5
4
3
2
0
Default
0
0
0
0
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
RX GO
RSVD
RXB16
IRQEN
RXB8
IRQEN
RXB1
IRQEN
RXBERR
IRQEN
RXC
IRQEN
RXE
IRQEN
Status bits are non-atomic (different flags may change value at different times in response to a single event).
Bit 7
Start Receive. Setting this bit causes the device to transition to receive mode. If necessary, the crystal oscillator and synthesizer
will start automatically after this bit is set. Firmware must never clear this bit. This bit must not be set until after it self clears. The
recommended method to exit receive mode when an error has occurred is to force END STATE and then dummy read all
RX_COUNT_ADR bytes from RX_BUFFER_ADR or poll RSSI_ADR.SOP (bit 7) until set. See XACT_CFG_ADR and
RX_ABORT_ADR for description.
Bit 6
Start of Packet Detect Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Bit 5
Buffer Full Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Bit 4
Buffer Half Empty Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Bit 3
Buffer Not Empty Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Bit 2
Buffer Error Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Bit 1
Packet Reception Complete Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Bit 0
Receive Error Interrupt Enable. See RX_IRQ_STATUS_ADR for description.
Mnemonic
RX_CFG_ADR
Address
1
0x06
Bit
7
6
5
4
3
2
0
Default
1
0
0
1
0
-
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
Function
AGC EN
LNA
ATT
HILO
FAST TURN
EN
Not Used
RXOW EN
VLD EN
Status bits are non-atomic (different flags may change value at different times in response to a single event).
Bit 7
Automatic Gain Control (AGC) Enable. When this bit is set, AGC is enabled, and the LNA is controlled by the AGC circuit.
When this bit is cleared the LNA is controlled manually using the LNA bit. Typical applications will clear this bit during initializa-
tion. It is recommended that this bit be disabled and bit 6 (LNA) be enabled unless the device will be used in a system where it
may receive data from a device using an external PA to transmit signals at >+4 dBm.
Bit 6
Low Noise Amplifier (LNA) Manual Control. When AGC EN (Bit 7) is cleared, this bit controls the state of the receiver LNA;
when AGC EN is set, this bit has no effect. Setting this bit enables the LNA; clearing this bit disables the LNA. Device current in
receive mode is slightly lower when the LNA is disabled. Typical applications will set this bit during initialization.
Bit 5
Receive Attenuator Enable. Setting this bit enables the receiver attenuator. The receiver attenuator may be used to desensitize
the receiver so that only very strong signals may be received. This bit should only be set when the AGC EN is disabled and the
LNA is manually disabled.
Bit 4
HILO. When FAST TURN EN is set, this bit is used to select whether the device will use the high frequency for the channel
selected, or the low frequency. 1 = hi; 0 = lo. When FAST TURN EN is not enabled this also controls the highlow bit to the
receiver and should be left at the default value of 1 for high side receive injection. Typical applications will clear this bit during
initialization.
Bit 3
Fast Turn Mode Enable. When this bit is set, the HILO bit determines whether the device receives data transmitted 1MHz
above the RX Synthesizer frequency or 1 MHz below the receiver synthesizer frequency. Use of this mode allows for very fast
turnaround, because the same synthesizer frequency may be used for both transmit and receive, thus eliminating the synthe-
sizer resettling period between transmit and receive. Note that when this bit is set, and the HILO bit is cleared, received data
bits are automatically inverted to compensate for the inversion of data received on the “image” frequency. Typical applications
will set this bit during initialization.
Bit 1
Overwrite Enable. When this bit is set, if an SOP is detected while the receive buffer is not empty, then the existing contents of
receive buffer are lost, and the new packet is loaded into the receive buffer. When this bit is set, the RXOW IRQ is enabled. If
this bit is cleared, then the receive buffer may not be overwritten by a new packet, and whenever the receive buffer is not empty
SOP conditions are ignored, and it is not possible to receive data until the previously received packet has been completely read
from the receive buffer.
Bit 0
Valid Flag Enable. When this bit is set, the receive buffer can store only 8 bytes of data. The other half of the buffer is used to
store valid flags. See RX_BUFFER_ADR for more detail.
[+] Feedback
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