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參數資料
| 型號： | CYRF69103 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | 可編程片上無線電低功耗 |
| 文件頁數： | 30/73頁 |
| 文件大?。?/td> | 683K |
| 代理商： | CYRF69103 |
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CYRF69103
Document #: 001-07611 Rev *B
Page 30 of 73
ECO Trim Register
General-Purpose I/O Ports
The general-purpose I/O ports are discussed in the following sections.
Port Data Registers
Table 41.ECO (ECO_TR) [0x1EB] [R/W]
Bit #
Field
Read/Write
Default
This register controls the ratios (in numbers of 32-KHz clock periods) of ‘on’ time versus ‘off’ time for LVD and POR detection circuit
Bits 7:6
Sleep Duty Cycle [1:0]
0 0 = 128 periods of the Internal 32-kHz Low-speed Oscillator
0 1 = 512 periods of the Internal 32-KHz Low-speed Oscillator
1 0 = 32 periods of the Internal 32-KHz Low-speed Oscillator
1 1 = 8 periods of the Internal 32-KHz Low-speed Oscillator
Note
This register can only be accessed in the second bank of I/O space. This requires setting the XIO bit in the CPU flags register
7
6
5
4
3
2
1
0
Sleep Duty Cycle [1:0]
R/W
0
Reserved
R/W
0
–
0
–
0
–
0
–
0
–
0
–
0
Table 42.P0 Data Register (P0DATA)[0x00] [R/W]
Bit #
Field
Read/Write
Default
This register contains the data for Port 0. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register
returns the current state of the Port 0 pins.
Bit 7
P0.7 Data
Bits 6:5
Reserved
Bits 4:3
P0.4–P0.3Data/INT2–INT0
In addition to their use as the P0.4–P0.2 GPIOs, these pins can also be used for the alternative functions as the Interrupt pins
(INT0–INT2). To configure the P0.4–P0.2 pins, refer to the P0.2/INT0–P0.4/INT2 Configuration Register (
Table 46
)
Bit 2
Reserved
Bit 1
P0.1 Data/Clock-output.
Bit 0
Reserved
7
6
5
4
3
2
1
0
P0.7
R/W
0
Reserved
-
P0.4/INT2
R/W
0
P0.3/INT1
R/W
0
Reserved
R/W
0
P0.1/CLKOUT
Reserved
-
-
-
-
-
Table 43.P1 Data Register (P1DATA) [0x01] [R/W]
Bit #
Field
Read/Write
Default
This register contains the data for Port 1. Writing to this register sets the bit values to be output on output enabled pins. Reading from this register
returns the current state of the Port 1 pins.
Bits 7:6
P1.7- P1.6
Bits 5:3
P1.5–P1.3 Data/SPI Pins (SMISO, SMOSI, SCLK, SSEL)
In addition to their use as the P1.6–P1.3 GPIOs, these pins can also be used for the alternative function as the SPI interface
pins. To configure the P1.6–P1.3 pins, refer to the P1.3–P1.6 Configuration Register (
Table 50
)
Bits 2:1
P1.2–P1.1
Bit 0
P1.0
7
6
5
4
3
2
1
0
P1.7
R/W
0
P1.6
R/W
0
P1.5/SMOSI
R/W
0
P1.4/SCLK
R/W
0
P1.3/SSEL
R/W
0
P1.2
R/W
0
P1.1
R/W
0
P1.0
R/W
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