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參數(shù)資料
| 型號(hào)： | CYRF69103 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | 可編程片上無線電低功耗 |
| 文件頁數(shù)： | 49/73頁 |
| 文件大小： | 683K |
| 代理商： | CYRF69103 |
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CYRF69103
Document #: 001-07611 Rev *B
Page 49 of 73
Mnemonic
TX_CFG_ADR
Address
0x03
Bit
7
6
5
4
3
2
1
0
Default
-
-
0
0
0
1
0
1
Read/Write
-
-
R/W
R/W
R/W
R/W
R/W
R/W
Function
Not Used
Not Used
Data Code
Length
Data Mode
PA Setting
Bit 5
Data Code Length. This bit selects the length of the DATA_CODE_ADR code for the data portion of the packet. This bit is
ignored when the data mode is set to GFSK. 1 = 64 chip codes. 0 = 32 chip codes.
Data Mode. This field sets the data transmission mode. 00 = 1-Mbps GFSK, 01 = 8DR Mode, 10 = DDR Mode, 11 = SDR Mode.
It is recommended that firmware sets the ALL SLOW bit in register ANALOG_CTRL_ADR when using GFSK data rate mode.
PA Setting. This field sets the transmit signal strength. 0 = –30 dBm, 1 = –25 dBm, 2 = –20 dBm, 3 = –15 dBm, 4 = –10 dBm,
5 = –5 dBm, 6 = 0 dBm, 7 = +4 dBm.
Bits 4:3
Bits 2:0
Mnemonic
TX_IRQ_STATUS_ADR
Address
0x04
Bit
7
6
5
4
3
2
1
0
Default
1
0
1
1
1
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Function
OS IRQ
LV IRQ
TXB15 IRQ
TXB8 IRQ
TXB0 IRQ
TXBERR IRQ
TXC IRQ
TXE IRQ
The state of all IRQ status bits is valid regardless of whether or not the IRQ is enabled. The IRQ output of the device is in its active state
whenever one or more bits in this register is set and the corresponding IRQ enable bit is also set. Status bits are non-atomic (different flags
may change value at different times in response to a single event). In particular, standard error handling is only effective if the premature
termination of a transmission due to an exception does not leave the device in an inconsistent state.
Bit 7
Oscillator Stable IRQ Status. This bit is set when the internal crystal oscillator has settled (synthesizer sequence starts).
Bit 6
Low Voltage Interrupt Status. This bit is set when the voltage on V
BAT
is below the LVI threshold (see PWR_CTL_ADR). This
interrupt is automatically disabled whenever the PMU is disabled. When enabled, this bit reflects the voltage on V
BAT
.
Bit 5
Buffer Not Full Interrupt Status. This bit is set whenever there are 15 or fewer bytes remaining in the transmit buffer.
Bit 4
Buffer Half Empty Interrupt Status. This bit is set whenever there are 8 or fewer bytes remaining in the transmit buffer.
Bit 3
Buffer Empty Interrupt Status. This bit is set at any time that the transmit buffer is empty.
Bit 2
Buffer Error Interrupt Status. This IRQ is triggered by either of two events: (1) When the transmit buffer (TX_BUFFER_ADR) is
empty and the number of bytes remaining to be transmitted is greater than zero; (2) When a byte is written to the transmit buffer
and the buffer is already full. This IRQ is cleared by setting bit TX CLR in TX_CTRL_ADR.
Bit 1
Transmission Complete Interrupt Status. This IRQ is triggered when transmission is complete. If transaction mode is not
enabled then this interrupt is triggered immediately after transmission of the last bit of the CRC16. If transaction mode is
enabled, this interrupt is triggered at the end of a transaction. Reading this register clears this bit. TXC IRQ and TXE IRQ flags
may change value at different times in response to a single event. If transaction mode is enabled and the first read of this regis-
ter returns TXC IRQ = 1 and TXE IRQ = 0 then firmware must execute a second read to this register to determine if an error
occurred by examining the status of TXE. There can be a case when this bit is not triggered when ACK EN = 1 and there is an
error in transmission. If the first read of this register returns TXC IRQ = 1 and TXE IRQ = 1 then the firmware must not execute
a second read to this register for a given transaction. If an ACK is received RXC IRQ and RXE IRQ may be asserted instead of
TXC IRQ and TXE IRQ.
Bit 0
Transmit Error Interrupt Status. This IRQ is triggered when there is an error in transmission. This interrupt is only applicable to
transaction mode. It is triggered whenever no valid ACK packet is received within the ACK timeout period. Reading this register
clears this bit.
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