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參數(shù)資料
| 型號： | CYRF69103 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | 可編程片上無線電低功耗 |
| 文件頁數(shù)： | 22/73頁 |
| 文件大?。?/td> | 683K |
| 代理商： | CYRF69103 |
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CYRF69103
Document #: 001-07611 Rev *B
Page 22 of 73
Interval Timer Clock (ITMRCLK)
The Interval Timer clock (ITMRCLK) can be sourced from the
internal 24-MHz oscillator, the internal 32-kHz low-power oscil-
lator, or the timer capture clock. A programmable prescaler of
1, 2, 3, or 4 then divides the selected source. The 12-bit
Programmable Interval Timer is a simple down counter with a
programmable reload value. It provides a 1-
μ
s resolution by
default. When the down counter reaches zero, the next clock
is spent reloading. The reload value can be read and written
while the counter is running, but care should be taken to
ensure that the counter does not unintentionally reload while
the 12-bit reload value is only partially stored—for example,
between the two writes of the 12-bit value. The programmable
interval timer generates interrupt to the CPU on each reload.
The parameters to be set will appear on the device editor view
of PSoC Designer once you place the enCoRe II timer user
module. The parameters are PITIMER_Source and
PITIMER_Divider. The PITIMER_Source is the clock to the
timer and the PITIMER_Divider is the value the clock is divided
by.
The interval register (PITMR) holds the value that is loaded
into the PIT counter on terminal count. The PIT counter is a
down counter.
The Programmable Interval Timer resolution is configurable.
For example:
TCAPCLK divide by x of CPU clock (for example TCAPCLK
divide by 2 of a 24-MHz CPU clock will give a frequency of
12 MHz)
ITMRCLK divide by x of TCAPCLK (for example, ITMRCLK
divide by 3 of TCAPCLK is 4 MHz so resolution is 0.25
μ
s).
Timer Capture Clock (TCAPCLK)
The Timer Capture clock (TCAPCLK) can be sourced from the
external crystal oscillator, internal 24-MHz oscillator or the
internal 32-kHz low-power oscillator. A programmable
prescaler of 2, 4, 6, or 8 then divides the selected source.
Table 34.Timer Clock Config (TMRCLKCR) [0x31] [R/W]
Bit #
Field
Read/Write
Default
Bits 7:6
7
TCAPCLK Divider
R/W
1
TCAPCLK Divider [1:0]
TCAPCLK Divider controls the TCAPCLK divisor
0 0 = Divider Value 2
0 1 = Divider Value 4
1 0 = Divider Value 6
1 1 = Divider Value 8
TCAPCLK Select
The TCAPCLK Select field controls the source of the TCAPCLK
0 0 = Internal 24-MHz Oscillator
0 1 =Reserved
1 0 = Internal 32-KHz Low-power Oscillator
1 1 = TCAPCLK Disabled
Note
The 1024-
μ
s interval timer is based on the assumption that TCAPCLK is running at 4 MHz. Changes in TCAPCLK frequency will cause a
corresponding change in the 1024-
μ
s interval timer frequency
Bits 3:2
ITMRCLK Divider
ITMRCLK Divider controls the ITMRCLK divisor
0 0 = Divider value of 1
0 1 = Divider value of 2
1 0 = Divider value of 3
1 1 = Divider value of 4
Bits 1:0
ITMRCLK Select
0 0 = Internal 24-MHz Oscillator
0 1 = Reserved
1 0 = Internal 32-KHz Low-power Oscillator
1 1 = TCAPCLK
Note
Changing the source of TMRCLK requires that both the source and destination clocks be running. Attempting to change the clock source
away from TCAPCLK after that clock has been stopped will not be successful
6
5
TCAPCLK Select
R/W
0
4
3
ITMRCLK Divider
R/W
1
2
1
ITMRCLK Select
R/W
1
0
R/W
0
R/W
0
R/W
1
R/W
1
Bits 5:4
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