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參數(shù)資料
| 型號： | CYRF69103 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | Programmable Radio on Chip Low Power |
| 中文描述： | 可編程片上無線電低功耗 |
| 文件頁數(shù)： | 34/73頁 |
| 文件大?。?/td> | 683K |
| 代理商： | CYRF69103 |
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CYRF69103
Document #: 001-07611 Rev *B
Page 34 of 73
Table 51.P1.4–P1.6 Configuration (P14CR–P16CR) [0x11–0x13] [R/W]
Bit #
Field
Read/Write
Default
These registers control the operation of pins P1.4–P1.6, respectively
The P1.4–P1.6 GPIO’s threshold is always set to TTL
When the SPI hardware is enabled, pins that are configured as SPI Use have their output enable and output state controlled by the SPI circuitry.
When the SPI hardware is disabled or a pin has its SPI Use bit clear, the pin is controlled by the Output Enable bit and the corresponding bit in
the P1 data register
Regardless of whether any pin is used as an SPI or GPIO pin the Int Enable, Int act Low, High Sink, Open Drain, and Pull-up Enable control the
behavior of the pin
The 50-mA sink drive capability is only available in the CY7C602xx. In the CY7C601xx, only 8-mA sink drive capability is available on this pin
regardless of the setting of the High Sink bit
Bit 7
SPI Use
0 = Disable the SPI alternate function. The pin is used as a GPIO
1 = Enable the SPI function. The SPI circuitry controls the output of the pin
Important Note for Comm Modes 01 or 10 (SPI Master or SPI Slave, see
Table 55
)
When configured for SPI (SPI Use = 1 and Comm Modes [1:0] = SPI Master or SPI Slave mode), the input/output direction of pins P1.3, P1.5,
and P1.6 is set automatically by the SPI logic. However, pin P1.4's input/output direction is NOT automatically set; it must be explicitly set by
firmware. For SPI Master mode, pin P1.4 must be configured as an output; for SPI Slave mode, pin P1.4 must be configured as an input
7
6
5
4
3
2
1
0
SPI Use
R/W
0
Int Enable
R/W
0
Int Act Low
R/W
0
Reserved
–
0
High Sink
R/W
0
Open Drain
R/W
0
Pull-up Enable Output Enable
R/W
0
R/W
0
Table 52. P1.7 Configuration (P17CR) [0x14] [R/W]
Bit #
Field
Read/Write
Default
This register controls the operation of pin P1.7
50-mA sink drive capability is available. The P1.7 GPIO’s threshold is always set to TTL
7
6
5
4
3
2
1
0
Reserved
–
0
Int Enable
R/W
0
Int Act Low
R/W
0
Reserved
–
0
High Sink
R/W
0
Open Drain
R/W
0
Pull-up Enable Output Enable
R/W
0
R/W
0
Table 53.P2 Configuration (P2CR) [0x15] [R/W]
Bit #
Field
Read/Write
Default
This register controls the operation of pins P2.0–P2.1
7
6
5
4
3
2
1
0
Reserved
–
0
Int Enable
R/W
0
Int Act Low
R/W
0
TTL Thresh
R/W
0
High Sink
R/W
0
Open Drain
R/W
0
Pull-up Enable Output Enable
R/W
0
R/W
0
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