參數(shù)資料
型號(hào): CYRF69103
廠商: Cypress Semiconductor Corp.
英文描述: Programmable Radio on Chip Low Power
中文描述: 可編程片上無線電低功耗
文件頁數(shù): 39/73頁
文件大?。?/td> 683K
代理商: CYRF69103
CYRF69103
Document #: 001-07611 Rev *B
Page 39 of 73
Table 59.Free-Running Timer High-Order Byte (FRTMRH) [0x21] [R/W]
Bit #
Field
Read/Write
Default
Bits 7:0
When reading the free-running timer, the low-order byte should be read first and the high-order second. When writing, the low-order byte should
be written first then the high-order byte.
7
6
5
4
3
2
1
0
Free-running Timer [15:8]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Free-running Timer [15:8]
Table 60.Programmable Interval Timer Low (PITMRL) [0x26] [R]
Bit #
Field
Read/Write
Default
Bits 7:0
This register holds the low order-byte of the 12-bit programmable interval timer. Reading this register causes the high-order byte to be moved
into a holding register allowing an automatic read of all 12 bits simultaneously
7
6
5
4
3
2
1
0
Prog Interval Timer [7:0]
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Prog Interval Timer [7:0]
Table 61.Programmable Interval Timer High (PITMRH) [0x27] [R]
Bit #
Field
Read/Write
Default
Bits 7:4
Bits 3:0
This register holds the high-order nibble of the 12-bit programmable interval timer. Reading this register returns the high-order nibble of the
12-bit timer at the instant that the low-order byte was last read
7
6
5
4
3
2
1
0
Reserved
Prog Interval Timer [11:8]
R
0
--
0
--
0
--
0
--
0
R
0
R
0
R
0
Reserved
Prog Internal Timer [11:8]
Table 62.Programmable Interval Reload Low (PIRL) [0x28] [R/W]
Bit #
Field
Read/Write
Default
Bits 7:0
This register holds the lower 8 bits of the timer. While writing into the 12-bit reload register, write lower byte first then the higher nibble.
7
6
5
4
Prog Interval [7:0]
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Prog Interval [7:0]
Table 63.Programmable Interval Reload High (PIRH) [0x29] [R/W]
Bit #
Field
Read/Write
Default
Bits 7:4]
Bits 3:0
This register holds the higher 4 bits of the timer. While writing into the 12-bit reload register, write lower byte first then the higher nibble
7
6
5
4
3
2
Prog Interval[11:8]
R/W
0
1
0
Reserved
--
0
--
0
--
0
--
0
R/W
0
R/W
0
R/W
0
Reserved
Prog Interval [11:8]
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