參數(shù)資料
型號(hào)： CYRF69103
廠商： Cypress Semiconductor Corp.
英文描述： Programmable Radio on Chip Low Power
中文描述： 可編程片上無(wú)線電低功耗
文件頁(yè)數(shù)： 41/73頁(yè)
文件大?。?/td> 683K
代理商： CYRF69103
CYRF69103
Document #: 001-07611 Rev *B
Page 41 of 73
Interrupt Controller
The interrupt controller and its associated registers allow the
user’s code to respond to an interrupt from almost every
functional block in the CYRF69103 devices. The registers
associated with the interrupt controller allow interrupts to be
disabled either globally or individually. The registers also
provide a mechanism by which a user may clear all pending
and posted interrupts, or clear individual posted or pending
interrupts.
The following table lists all interrupts and the priorities that are
available in the CYRF69103.
Architectural Description
An interrupt is posted when its interrupt conditions occur. This
results in the flip-flop in
Figure 18
clocking in a ‘1’. The
interrupt will remain posted until the interrupt is taken or until
it is cleared by writing to the appropriate INT_CLRx register.
A posted interrupt is not pending unless it is enabled by setting
its interrupt mask bit (in the appropriate INT_MSKx register).
All pending interrupts are processed by the Priority Encoder to
determine the highest priority interrupt which will be taken by
the M8C if the Global Interrupt Enable bit is set in the CPU_F
register.
Disabling an interrupt by clearing its interrupt mask bit (in the
INT_MSKx register) does not clear a posted interrupt, nor
does it prevent an interrupt from being posted. It simply
prevents a posted interrupt from becoming pending.
Nested interrupts can be accomplished by reenabling inter-
rupts inside an interrupt service routine. To do this, set the IE
bit in the Flag Register.
A block diagram of the CYRF69103 Interrupt Controller is
shown in
Figure 18
.
Figure 18. Interrupt Controller Block Diagram
Table 64.Interrupt Priorities, Address, Name
Interrupt
Priority
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Interrupt
Address
0000h
0004h
0008h
000Ch
0010h
0014h
0018h
001Ch
0020h
0024h
0028h
002Ch
0030h
0034h
0038h
003Ch
0040h
Name
Reset
POR/LVD
Reserved
SPI Transmitter Empty
SPI Receiver Full
GPIO Port 0
GPIO Port 1
INT1
Reserved
Reserved
Reserved
Reserved
Reserved
1-ms Interval timer
Programmable Interval Timer
Reserved
Reserved
17
18
19
20
21
22
23
24
25
0044h
0048h
004Ch
0050h
0054h
0058h
005Ch
0060h
0064h
16-bit Free Running Timer Wrap
INT2
Reserved
GPIO Port 2
Reserved
Reserved
Reserved
Reserved
Sleep Timer
Table 64.Interrupt Priorities, Address, Name
(continued)
Interrupt
Priority
Interrupt
Address
Name
Interrupt
Source
(Timer,
GPIO, etc.)
Interrupt Taken
or
INT_CLRx Write
Posted
Interrupt
Pending
Interrupt
GIE
Interrupt Vector
Mask Bit Setting
D
R
Q
1
Priority
Encoder
M8C Core
Interrupt
Request
.
.
INT_MSKx
CPU_F[0]
[+] Feedback
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