參數(shù)資料
型號(hào)： ARM610
廠商： Mitel Networks Corporation
英文描述： General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲(chǔ)器管理單元）)
中文描述： 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲(chǔ)器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲(chǔ)器管理單元））
文件頁數(shù)： 97/174頁
文件大?。?/td> 694K
代理商： ARM610
Instruction and Data Cache (IDC)
ARM610 Data Sheet
6-3
6.4.2 Uncacheable reads
C = 0
The cache is not searched for the relevant data; instead an external memory access
is initiated. No linefetch operation is performed, and the cache is not updated.
6.4.3 Updateable writes
U = 1
An external memory access is initiated, and the cache is searched; if the cache holds
a copy of the data from the address being written to, then the cache data is
simultaneously updated.
6.4.4 Non-updateable writes
U = 0
An external memory access is initiated, but the cache is not searched and the contents
of the cache are not affected.
6.5
IDC Validity
The IDC operates with virtual addresses, so care must be taken to ensure that its
contents remain consistent with the virtual to physical mappings performed by the
Memory Management Unit. If the Memory Mappings are changed, the IDC validity
must be ensured.
6.5.1 Software IDC flush
The entire IDC may be marked as invalid by writing to the ARM610 IDC Flush Register
(Register 7). The cache will be flushed immediately the register is written, but note that
the following two instruction fetches may come from the cache before the register is
written.
6.5.2 Doubly mapped space
Since the cache works with virtual addresses, it is assumed that every virtual address
maps to a different physical address. If the same physical location is accessed by more
than one virtual address, the cache cannot maintain consistency, since each virtual
address will have a separate entry in the cache, and only one entry will be updated on
a processor write operation. To avoid any cache inconsistencies, both doubly-mapped
virtual addresses should be marked as uncacheable.
6.6
Read-Lock-Write
The IDC treats the Read-Locked-Write instruction as a special case. The read phase
always forces a read of external memory, regardless of whether the data is contained
in the cache. The write phase is treated as a normal write operation (and if marked as
updateable, and the data is already in the cache, the cache will be updated). Externally
the two phases are flagged as indivisible by asserting the
LOCK
signal.
相關(guān)PDF資料
PDF描述
ARRAYS NIGHT VISION H.V. RECTIFIER DIODES & ARRAYS
ARS2540 40A GLASS PASSIVATED AVALANCHE BUTTON DIODE
AR2540 40A GLASS PASSIVATED AVALANCHE BUTTON DIODE
ARS25A 25A AUTOMOTIVE BUTTON DIODE
ARS25J 25A AUTOMOTIVE BUTTON DIODE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ARM7-009 制造商:Gravitech 功能描述:ARM7 LPC2378 W/2.8" TCH SCRN LCD BLU
ARM720T 制造商:未知廠家 制造商全稱:未知廠家 功能描述:General-purpose 32-bit Microprocessor with 8KB cache, enlarged Write buffer, and Memory Management Unit (MMU) combined in a single chip
ARM7DIMM-LPC2478 功能描述:模塊化系統(tǒng) - SOM LPC2478 ARM7 DIMM Module, Rev 2.2 RoHS:否 制造商:Digi International 外觀尺寸:ConnectCore 9P 處理器類型:ARM926EJ-S 頻率:150 MHz 存儲(chǔ)容量:8 MB, 16 MB 存儲(chǔ)類型:NOR Flash, SDRAM 接口類型:I2C, SPI, UART 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 尺寸:1.97 in x 1.97 in x 6.1 in
ARM7TDI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:周立功的中文ARM7TDI文檔
ARM7TDMI 制造商:未知廠家 制造商全稱:未知廠家 功能描述:general purpose 32-bit microprocessors
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*