參數(shù)資料
型號： ARM610
廠商： Mitel Networks Corporation
英文描述： General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲器管理單元）)
中文描述： 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲器管理單元））
文件頁數(shù)： 26/174頁
文件大?。?/td> 694K
代理商： ARM610
Programmer’s Model
ARM610 Data Sheet
3-10
3.5.7 Exception priorities
When multiple exceptions arise at the same time, a fixed priority system determines
the order in which they will be handled:
1
Reset (highest priority)
2
Data abort
3
FIQ
4
IRQ
5
Prefetch abort
6
Undefined Instruction, Software interrupt (lowest priority)
Note that not all exceptions can occur at once. Undefined instruction and software
interrupt are mutually exclusive since they each correspond to particular (non-
overlapping) decodings of the current instruction.
If a data abort
occurs at the same time as a FIQ, and FIQs are enabled (i.e. the F flag
in the CPSR is clear), ARM610 will enter the data abort handler and then immediately
proceed to the FIQ vector. A normal return from FIQ will cause the data abort handler
to resume execution. Placing data abort at a higher priority than FIQ is necessary to
ensure that the transfer error does not escape detection; the time for this exception
entry should be added to worst case FIQ latency calculations.
3.5.8 Interrupt latencies
Calculating the worst case interrupt latency for the ARM610 is quite complex due to
the cache, MMU and write buffer and is dependant on the configuration of the whole
system. Please see Application Note - Calculating the ARM610 Interrupt Latency.
3.6
Reset
When the
nRESET
signal goes LOW, ARM610 abandons the executing instruction
and then performs idle cycles from incrementing word addresses. At the end of the
reset sequence ARM610 performs either 1 or 2 memory accesses from the address
reached before
nRESET
goes HIGH.
When
nRESET
goes HIGH again, ARM610 performs the following:
1
Overwrites R14_svc and SPSR_svc by copying the current values of the PC
and CPSR into them. The value of the saved PC and CPSR is not defined.
2
Forces M[4:0]=10011 (Supervisor mode) and sets the I and F bits in the
CPSR.
3
Performs either one or two memory accesses from the address output at the
end of the reset.
4
Forces the PC to fetch the next instruction from address 0x00
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