參數(shù)資料
型號： ARM610
廠商： Mitel Networks Corporation
英文描述： General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲器管理單元）)
中文描述： 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲器管理單元））
文件頁數(shù)： 71/174頁
文件大?。?/td> 694K
代理商： ARM610
Instruction Set - SWP
ARM610 Data Sheet
4-43
O
4.10 Single Data Swap (SWP)
Figure 4-21: Swap instruction
The instruction is only executed if the condition is true. The various conditions are
defined in
·
Table 4-2: Condition code summaryon page 4-6. The instruction encoding
is shown in
·
Figure 4-21: Swap instruction
The data swap instruction is used to swap a byte or word quantity between a register
and external memory. This instruction is implemented as a memory read followed by
a memory write which are “l(fā)ocked” together (the processor cannot be interrupted until
both operations have completed, and the memory manager is warned to treat them as
inseparable). This class of instruction is particularly useful for implementing software
semaphores.
The swap address is determined by the contents of the base register (Rn). The
processor first reads the contents of the swap address. Then it writes the contents of
the source register (Rm) to the swap address, and stores the old memory contents in
the destination register (Rd). The same register may be specified as both the source
and destination.
The
LOCK
output goes HIGH for the duration of the read and write operations to signal
to the external memory manager that they are locked together, and should be allowed
to complete without interruption. This is important in multi-processor systems where
the swap instruction is the only indivisible instruction which may be used to implement
semaphores; control of the memory must not be removed from a processor while it is
performing a locked operation.
4.10.1 Bytes and words
This instruction class may be used to swap a byte (B=1) or a word (B=0) between an
ARM610 register and memory. The SWP instruction is implemented as a LDR followed
by a STR and the action of these is as described in the section on single data transfers.
In particular, the description of big and little-endian configuration applies to the SWP
instruction.
31
28 27
23
22
21
20 19
16 15
12 11
8
7
4
3
0
Cond
00010
B
00
Rn
Rd
0000
1001
Rm
Source register
Destination register
Base register
Byte/Word bit
0 = Swap word quantity
1 = Swap byte quantity
Condition field
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