參數(shù)資料
型號： ARM610
廠商： Mitel Networks Corporation
英文描述： General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲器管理單元）)
中文描述： 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲器管理單元））
文件頁數(shù)： 45/174頁
文件大?。?/td> 694K
代理商： ARM610
Instruction Set - MRS, MSR
ARM610 Data Sheet
4-17
O
4.5
PSR Transfer (MRS, MSR)
The instruction is only executed if the condition is true. The various conditions are
defined in
·
Table 4-2: Condition code summaryon page 4-6.
The MRS and MSR instructions are formed from a subset of the Data Processing
operations and are implemented using the TEQ, TST, CMN and CMP instructions
without the S flag set. The encoding is shown in
·
Figure 4-10: PSR transferon page
4-18.
These instructions allow access to the CPSR and SPSR registers. The MRS
instruction allows the contents of the CPSR or SPSR_<mode> to be moved to a
general register. The MSR instruction allows the contents of a general register to be
moved to the CPSR or SPSR_<mode> register.
The MSR instruction also allows an immediate value or register contents to be
transferred to the condition code flags (N,Z,C and V) of CPSR or SPSR_<mode>
without affecting the control bits. In this case, the top four bits of the specified register
contents or 32-bit immediate value are written to the top four bits of the relevant PSR.
4.5.1 Operand restrictions
In User mode, the control bits of the CPSR are protected from change, so only
the condition code flags of the CPSR can be changed. In other (privileged)
modes the entire CPSR can be changed.
Note that the software must never change the state of the T bit in the CPSR.
If this happens, the processor will enter an unpredictable state.
The SPSR register which is accessed depends on the mode at the time of
execution. For example, only SPSR_fiq is accessible when the processor is in
FIQ mode.
You must not specify R15 as the source or destination register.
Also, do not attempt to access an SPSR in User mode, since no such register
exists.
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