參數(shù)資料
型號(hào)： ARM610
廠商： Mitel Networks Corporation
英文描述： General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲(chǔ)器管理單元）)
中文描述： 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲(chǔ)器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲(chǔ)器管理單元））
文件頁數(shù)： 59/174頁
文件大?。?/td> 694K
代理商： ARM610
Instruction Set - LDR, STR
ARM610 Data Sheet
4-31
O
Figure 4-15: Halfword and signed data transfer with immediate offset
4.8.1 Offsets and auto-indexing
The offset from the base may be either a 8-bit unsigned binary immediate value in the
instruction, or a second register. The 8-bit offset is formed by concatenating bits 11 to
8 and bits 3 to 0 of the instruction word, such that bit 11 becomes the MSB and bit 0
becomes the LSB. The offset may be added to (U=1) or subtracted from (U=0) the
base register Rn. The offset modification may be performed either before (pre-indexed,
P=1) or after (post-indexed, P=0) the base register is used as the transfer address.
The W bit gives optional auto-increment and decrement addressing modes. The
modified base value may be written back into the base (W=1), or the old base may be
kept (W=0). In the case of post-indexed addressing, the write back bit is redundant and
is always set to zero, since the old base value can be retained if necessary by setting
the offset to zero. Therefore post-indexed data transfers always write back the modified
base.
The Write-back bit should not be set high (W=1) when post-indexed addressing is
selected.
Immediate Offset
(Low nibble)
S H
00 = SWP instruction
01 = Unsigned halfwords
10 = Signed byte
11 = Signed halfwords
Immediate Offset
(High nibble)
Source/Destination register
Base register
Load/Store
0 = Store to memory
1 = Load from memory
Write-back
0 = No write-back
1 = Write address into base
Up/Down
0 = Down: subtract offset from base
1 = Up: add offset to base
Pre/Post indexing
0 = Post: add/subtract offset after transfer
1 = Pre: add/subtract offset before transfer
31
28 27
25
24
23
22
21
20 19
16 15
12 11
8
7
6
5
4
3
0
Cond
0
0
0
P
U
1
W
L
Rn
Rd
Offset
1
S H
1
Offset
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