參數(shù)資料
型號： ARM610
廠商： Mitel Networks Corporation
英文描述： General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲器管理單元）)
中文描述： 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲器管理單元））
文件頁數(shù)： 20/174頁
文件大小： 694K
代理商： ARM610
Programmer’s Model
ARM610 Data Sheet
3-4
Figure 3-1: Register organisation
FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). Many FIQ
programs will not need to save any registers. User mode, IRQ mode, Supervisor
mode,
Abort mode and Undefined mode each have two banked registers mapped to
R13 and R14. The two banked registers allow these modes to each have a private
which require more than these two banked registers are expected to save some or all
of the caller's registers (R0 to R12) on their respective stacks. They are then free to
use these registers which they will restore before returning to the caller. In addition
there are also five SPSRs (Saved Program Status Registers) which are loaded with
the CPSR when an exception occurs. There is one SPSR for each privileged mode.
Abort and Undefined mode programs
General Registers and Program Counter Modes
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15 (PC)
R0
R1
R2
R3
R4
R5
R6
R7
R8_fiq
R9_fiq
R10_fiq
R11_fiq
R12_fiq
R13_fiq
R14_fiq
R15 (PC)
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_svc
R14_svc
R15 (PC)
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_abt
R14_abt
R15 (PC)
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_irq
R14_irq
R15 (PC)
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_und
R14_und
R15 (PC)
User32
FIQ32
Supervisor32
Abort32
IRQ32
Undefined32
CPSR
CPSR
SPSR_fiq
CPSR
SPSR_svc
CPSR
SPSR_abt
CPSR
SPSR_irq
CPSR
SPSR_und
Program Status Registers
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