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| 型號(hào)： | ARM610 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲(chǔ)器管理單元）) |
| 中文描述： | 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲(chǔ)器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲(chǔ)器管理單元）） |
| 文件頁(yè)數(shù)： | 19/174頁(yè) |
| 文件大?。?/td> | 694K |
| 代理商： | ARM610 |
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Programmer’s Model
ARM610 Data Sheet
3-3
3.3
Operating Mode Selection
ARM610 has a 32-bit data bus and a 32-bit address bus. The data types the processor
supports are Bytes (8 bits) and Words (32 bits), where words must be aligned to four
byte boundaries. Instructions are exactly one word, and data operations (e.g. ADD)
are only performed on word quantities. Load and store operations can transfer either
bytes or words.
ARM610 supports six modes of operation:
1
User mode (usr): the normal program execution state
2
FIQ mode (fiq): designed to support a data transfer or channel process
3
IRQ mode (irq): used for general purpose interrupt handling
4
Supervisor mode (svc): a protected mode for the operating system
5
Abort mode (abt): entered after a data or instruction prefetch
abort
6
Undefined mode (und): entered when an undefined instruction is executed
Mode changes may be made under software control or may be brought about by
external interrupts or exception processing. Most application programs will execute in
User mode. The other modes, known as
privileged modes
interrupts or exceptions or to access protected resources.
, will be entered to service
3.4
Registers
The processor has a total of 37 registers made up of 31 general 32-bit registers and
6 status registers. At any one time 16 general registers (R0 to R15) and one or two
status registers are visible to the programmer. The visible registers depend on the
processor mode and the other registers (the
support IRQ, FIQ, Supervisor,
Abort and Undefined mode processing. The register
bank organisation is shown in
·
Figure 3-1: Register organisation
banked registers are shaded in the diagram.
banked registers
) are switched in to
on page 3-4. The
In all modes 16 registers, R0 to R15, are directly accessible. All registers except R15
are general purpose and may be used to hold data or address values. Register R15
holds the Program Counter (PC). When R15 is read, bits [1:0] are zero and bits [31:2]
contain the PC. A seventeenth register (the CPSR - Current Program Status Register)
is also accessible. It contains condition code flags and the current mode bits and may
be thought of as an extension to the PC.
R14 is used as the subroutine link register and receives a copy of R15 when a Branch
and Link instruction is executed. It may be treated as a general purpose register at all
other times. R14_svc, R14_irq, R14_fiq, R14_abt and R14_und are used similarly to
hold the return values of R15 when interrupts and exceptions arise, or when Branch
and Link instructions are executed within interrupt or exception routines.
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