參數(shù)資料
型號： ARM610
廠商： Mitel Networks Corporation
英文描述： General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲器管理單元）)
中文描述： 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲器管理單元））
文件頁數(shù)： 107/174頁
文件大小： 694K
代理商： ARM610
Memory Management Unit
ARM610 Data Sheet
9-3
Translation Table Base Register
This holds the physical address of the base of the translation table maintained in main
memory. Note that this base must reside on a 16Kb boundary.
Domain Access Control Register
This consists of sixteen 2-bit fields, each of which defines the access permissions for
one of the sixteen Domains (D15-D0).
Note
The registers not shown are reserved and should not be used.
Fault Status Register
This indicates the domain and type of access being attempted when an abort
occurred. Bits 7:4 specify which of the sixteen domains (D15-D0) was being accessed
when a fault occurred. Bits 3:1 indicate the type of access being attempted. The
encoding of these bits is different for internal and external faults (as indicated by bit 0
in the register) and is shown in
·
Table 9-4: Priority encoding of fault status
9-12. A write to this register flushes the TLB.
on page
Fault Address Register
This holds the virtual address of the access which was attempted when a fault
occurred. A write to this register causes the data written to be treated as an address
and, if it is found in the TLB, the entry is marked as invalid. (This operation is known
as a TLB purge). The Fault Status Register and Fault Address Register are only
updated for data faults, not for prefetch faults.
9.3
Address Translation
The MMU translates virtual addresses generated by the CPU into physical addresses
to access external memory, and also derives and checks the access permission.
Translation information, which consists of both the address translation data and the
Domain Access Control
8
9
0
Control
L D P W
A
C
M
Translation Table Base
0
1
2
3
4
5
6
7
10
11
12
13
14
15
0 0 0 0
Domain
Status
0
1
2
3
4
5
6
7
8
S B
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Flush TLB
Purge Address
Fault Address
Register
1
write
2
write
3
write
5
read
5
write
6
read
6
write
Fault Status
Figure 9-1: MMU register summary
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