參數(shù)資料
型號(hào)： ARM610
廠商： Mitel Networks Corporation
英文描述： General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲(chǔ)器管理單元）)
中文描述： 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲(chǔ)器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲(chǔ)器管理單元））
文件頁數(shù)： 81/174頁
文件大?。?/td> 694K
代理商： ARM610
Instruction Set - MRC, MCR
ARM610 Data Sheet
4-53
O
4.14 Coprocessor Register Transfers (MRC, MCR)
The instruction is only executed if the condition is true. The various conditions are
defined in
·
Table 4-2: Condition code summaryon page 4-6. The instruction encoding
is shown in
·
Figure 4-25: Coprocessor register transfer instructions
This class of instruction is used to communicate information directly between ARM610
and a coprocessor. An example of a coprocessor to ARM610 register transfer (MRC)
instruction would be a FIX of a floating point value held in a coprocessor, where the
floating point number is converted into a 32-bit integer within the coprocessor, and the
result is then transferred to ARM610 register. A FLOAT of a 32-bit value in ARM610
register into a floating point value within the coprocessor illustrates the use of ARM610
register to coprocessor transfer (MCR).
An important use of this instruction is to communicate control information directly from
the coprocessor into the ARM610 CPSR flags. As an example, the result of a
comparison of two floating point values within a coprocessor can be moved to the
CPSR to control the subsequent flow of execution.
Figure 4-25: Coprocessor register transfer instructions
4.14.1 The coprocessor fields
The CP# field is used, as for all coprocessor instructions, to specify which coprocessor
is being called upon.
The CP Opc, CRn, CP and CRm fields are used only by the coprocessor, and the
interpretation presented here is derived from convention only. Other interpretations
are allowed where the coprocessor functionality is incompatible with this one. The
conventional interpretation is that the CP Opc and CP fields specify the operation the
coprocessor is required to perform, CRn is the coprocessor register which is the
source or destination of the transferred information, and CRm is a second coprocessor
register which may be involved in some way which depends on the particular operation
specified.
31
28 27
24
23
21
20 19
16 15
12 11
8
7
5
4
3
0
Cond
1110
CP Opc
L
CRn
Rd
CP#
CP
1
CRm
Coprocessor operand register
Coprocessor information
Coprocessor number
ARM source/destination register
Coprocessor source/destination
Load/Store bit
0 = Store to coprocessor
1 = Load from coprocessor
Coprocessor operation mode
Condition field
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