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參數(shù)資料
| 型號： | ARM610 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲器管理單元）) |
| 中文描述： | 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲器管理單元）） |
| 文件頁數(shù)： | 139/174頁 |
| 文件大?。?/td> | 694K |
| 代理商： | ARM610 |
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Boundary-Scan Test Interface
ARM610 Data Sheet
11-5
In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-
DR state, test data is shifted into the bypass register via
delay of one
TCK
cycle. The first bit shifted out will be a zero. The bypass register is
not affected in the UPDATE-DR state.
TDI
and out via
TDO
after a
11.6.4 HIGHZ (0111)
The HIGHZ instruction connects a 1–bit shift register (the BYPASS register) between
TDI
and
TDO
.
When the HIGHZ instruction is loaded into the instruction register, all outputs are
placed in an inactive drive state.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-
DR state, test data is shifted into the bypass register via
delay of one
TCK
cycle. The first bit shifted out will be a zero. The bypass register is
not affected in the UPDATE-DR state.
TDI
and out via
TDO
after a
11.6.5 CLAMPZ (1001)
The CLAMPZ instruction connects a 1–bit shift register (the BYPASS register)
between
TDI
and
TDO
.
When the CLAMPZ instruction is loaded into the instruction register, all outputs are
placed in an inactive drive state, but the data supplied to the disabled output drivers is
derived from the boundary-scan cells. The purpose of this instruction is to ensure,
during production testing, that each output driver can be disabled when its data input
is either a 0 or a 1.
A guarding pattern (specified for this device at the end of this section) should be pre-
loaded into the boundary-scan register using the SAMPLE/PRELOAD instruction prior
to selecting the CLAMPZ instruction.
In the CAPTURE-DR state, a logic 0 is captured by the bypass register. In the SHIFT-
DR state, test data is shifted into the bypass register via
delay of one
TCK
cycle. The first bit shifted out will be a zero. The bypass register is
not affected in the UPDATE-DR state.
TDI
and out via
TDO
after a
11.6.6 INTEST (1100)
The BS (boundary-scan) register is placed in test mode by the INTEST instruction.
The INTEST instruction connects the BS register between
TDI
and
TDO
.
When the instruction register is loaded with the INTEST instruction, all the boundary-
scan cells are placed in their test mode of operation.
In the CAPTURE-DR state, the complement of the data supplied to the core logic from
input boundary-scan cells is captured, while the true value of the data that is output
from the core logic to output boundary- scan cells is captured. CAPTURE-DR captures
the complemented value of the input cells for testability reasons.
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