參數(shù)資料
型號： ARM610
廠商： Mitel Networks Corporation
英文描述： General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲器管理單元）)
中文描述： 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲器管理單元））
文件頁數(shù)： 78/174頁
文件大?。?/td> 694K
代理商： ARM610
Instruction Set - LDC, STC
ARM610 Data Sheet
4-50
O
4.13.2 Addressing modes
ARM610 is responsible for providing the address used by the memory system for the
transfer, and the addressing modes available are a subset of those used in single data
transfer instructions. Note, however, that the immediate offsets are 8 bits wide and
specify word offsets for coprocessor data transfers, whereas they are 12 bits wide and
specify byte offsets for single data transfers.
The 8-bit unsigned immediate offset is shifted left 2 bits and either added to (U=1) or
subtracted from (U=0) the base register (Rn); this calculation may be performed either
before (P=1) or after (P=0) the base is used as the transfer address. The modified base
value may be overwritten back into the base register (if W=1), or the old value of the
base may be preserved (W=0). Note that post-indexed addressing modes require
explicit setting of the W bit, unlike LDR and STR which always write-back when post-
indexed.
The value of the base register, modified by the offset in a pre-indexed instruction, is
used as the address for the transfer of the first word. The second word (if more than
one is transferred) will go to or come from an address one word (4 bytes) higher than
the first transfer, and the address will be incremented by one word for each subsequent
transfer.
4.13.3 Address alignment
The base address should normally be a word-aligned quantity. The bottom 2 bits of the
address will appear on
A[1:0]
and might be interpreted by the memory system.
4.13.4 Use of R15
If Rn is R15, the value used will be the address of the instruction plus 8 bytes. Base
write-back to R15 must not be specified.
4.13.5 Data aborts
If the address is legal but the memory manager generates an abort, the data trap will
be taken. The writeback of the modified base will take place, but all other processor
state will be preserved. The coprocessor is partly responsible for ensuring that the
data transfer can be restarted after the cause of the
abort has been resolved, and must
ensure that any subsequent actions it undertakes can be repeated when the
instruction is retried.
4.13.6 Instruction cycle times
Coprocessor data transfer instructions take (n-1)S + 2N + bI incremental cycles to
execute, where:
n
is the number of words transferred.
b
is the number of cycles spent in the coprocessor busy-wait loop.
S, N and I are as defined in
·
6.2 Cycle Typeson page 6-2.
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