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參數(shù)資料
| 型號： | ARM610 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲器管理單元）) |
| 中文描述： | 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲器管理單元）） |
| 文件頁數(shù)： | 68/174頁 |
| 文件大?。?/td> | 694K |
| 代理商： | ARM610 |
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Instruction Set - LDM, STM
ARM610 Data Sheet
4-40
O
4.9.5 Use of R15 as the base
R15 should not be used as the base register in any LDM or STM instruction.
4.9.6 Inclusion of the base in the register list
When write-back is specified, the base is written back at the end of the second cycle
of the instruction. During a STM, the first register is written out at the start of the
second cycle. A STM which includes storing the base, with the base as the first register
to be stored, will therefore store the unchanged value, whereas with the base second
or later in the transfer order, will store the modified value. A LDM will always overwrite
the updated base if the base is in the list.
4.9.7 Data aborts
Some legal addresses may be unacceptable to a memory management system, and
the memory manager can indicate a problem with an address by taking the
ABORT
signal HIGH. This can happen on any transfer during a multiple register load or store,
and must be recoverable if ARM610 is to be used in a virtual memory system.
Aborts during STM instructions
If the
abort occurs during a store multiple instruction, ARM610 takes little action until
the instruction completes, whereupon it enters the data abort trap. The memory
manager is responsible for preventing erroneous writes to the memory. The only
change to the internal state of the processor will be the modification of the base
register if write-back was specified, and this must be reversed by software (and the
cause of the
abort resolved) before the instruction may be retried.
Aborts during LDM instructions
When ARM610 detects a data abort during a load multiple instruction, it modifies the
operation of the instruction to ensure that recovery is possible.
1
Overwriting of registers stops when the abort happens. The
aborting load will
not take place but earlier ones may have overwritten registers. The PC is
always the last register to be written and so will always be preserved.
2
The base register is restored, to its modified value if write-back was
requested. This ensures recoverability in the case where the base register is
also in the transfer list, and may have been overwritten before the
abort
occurred.
The data abort
trap is taken when the load multiple has completed, and the system
software must undo any base modification (and resolve the cause of the abort) before
restarting the instruction.
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