參數(shù)資料
型號： ARM610
廠商： Mitel Networks Corporation
英文描述： General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲器管理單元）)
中文描述： 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲器管理單元））
文件頁數(shù)： 64/174頁
文件大?。?/td> 694K
代理商： ARM610
Instruction Set - LDM, STM
ARM610 Data Sheet
4-36
O
4.9
Block Data Transfer (LDM, STM)
The instruction is only executed if the condition is true. The various conditions are
defined in
·
Table 4-2: Condition code summaryon page 4-6. The instruction encoding
is shown in
·
Figure 4-16: Block data transfer instructions
Block data transfer instructions are used to load (LDM) or store (STM) any subset of
the currently visible registers. They support all possible stacking modes, maintaining
full or empty stacks which can grow up or down memory, and are very efficient
instructions for saving or restoring context, or for moving large blocks of data around
main memory.
4.9.1 The register list
The instruction can cause the transfer of any registers in the current bank (and
non-user mode programs can also transfer to and from the user bank, see below). The
register list is a 16-bit field in the instruction, with each bit corresponding to a register.
A 1 in bit 0 of the register field will cause R0 to be transferred, a 0 will cause it not to
be transferred; similarly bit 1 controls the transfer of R1, and so on.
Any subset of the registers, or all the registers, may be specified. The only restriction
is that the register list should not be empty.
Whenever R15 is stored to memory the stored value is the address of the STM
instruction plus 12.
Figure 4-16: Block data transfer instructions
31
28 27
25
24
23
22
21
20 19
16 15
0
Cond
100
P
U
S
W
L
Rn
Register list
Base register
Load/Store bit
0 = Store to memory
1 = Load from memory
Write-back bit
0 = No write-back
1 = Write address into base
PSR and force user bit
0 = Do not load PSR or force user mode
1 = Load PSR or force user mode
Up/Down bit
0 = Down; subtract offset from base
1 = Up; add offset from base
Pre/Post indexing bit
0 = Post; add offset after transfer
1 = Pre; add offset before transfer
Condition field
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