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參數(shù)資料
| 型號(hào)： | ARM610 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫(xiě)緩沖器和存儲(chǔ)器管理單元）) |
| 中文描述： | 通用32位微處理器4KB的高速緩存，寫(xiě)緩沖器和存儲(chǔ)器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫(xiě)緩沖器和存儲(chǔ)器管理單元）） |
| 文件頁(yè)數(shù)： | 15/174頁(yè) |
| 文件大?。?/td> | 694K |
| 代理商： | ARM610 |
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Signal Description
ARM610 Data Sheet
2-3
MSE
IT
Memory request/sequential enable. When this input is LOW, the
and
SEQ
outputs are put into a high impedance state (Note 1).
nMREQ
nBW
OCZ
Not byte / word. An output signal used by the processor to indicate to the
external memory system when a data transfer of a byte length is required.
nBW
is HIGH for word transfers and LOW for byte transfers, and is valid for
both read and write operations. The signal changes while
nBW
is latched by
ALE
.
MCLK
is HIGH.
nFIQ
IT
Not fast interrupt request. If FIQs are enabled, the processor will respond
to a LOW level on this input by taking the FIQ interrupt exception. This is an
asynchronous, level-sensitive input, and must be held LOW until a suitable
response is received from the processor.
nIRQ
IT
Not interrupt request. As
asynchronously to interrupt the processor when the IRQ enable is active.
nFIQ
, but with lower priority. May be taken LOW
nMREQ
OCZ
Not memory request. A pipelined signal that changes while
to indicate whether or not in the following cycle, the processor will be
accessing external memory. When
accessing external memory.
MCLK
is LOW
nMREQ
is LOW, the processor will be
nRESET
IT
Not reset. This is a level sensitive input which is used to start the processor
from a known address. A LOW level will cause the current instruction to
terminate abnormally, and the on-chip cache, MMU, and write buffer to be
disabled. When
nRESET
is driven HIGH, the processor will re-start from
address 0.
nRESET
must remain LOW for at least two full
five full
MCLK
cycles whichever is greater. While
processor will perform idle cycles with incrementing addresses and
must be HIGH.
FCLK
is LOW the
cycles or
nRESET
nWAIT
nRW
OCZ
Not read/write. When HIGH this signal indicates a processor write
operation; when LOW, a read. The signal changes while
nRW
is latched by
ALE
.
MCLK
is HIGH.
nTRST
IT
Test interface reset. Note this pin does NOT have an internal pullup
resistor. This pin must be pulsed or driven LOW to achieve normal device
operation, in addition to the normal device reset (
nRESET
).
nWAIT
IT
Not wait. When LOW this allows extra
memory accesses. It must change during the LOW phase of the
cycle to be extended.
MCLK
cycles to be inserted in
MCLK
SEQ
OCZ
Sequential address. This signal is the inverse of
for compatibility with existing ARM memory systems.
nMREQ
, and is provided
SnA
IT
This pin should be hard wired HIGH.
TEST
IN[16:0]
IT
Test bus input. This bus is used for off-board testing of the device. When
the device is fitted to a circuit all these pins must be tied LOW.
Name
Type
Description
Table 2-1: Signal descriptions (Continued)
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