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參數(shù)資料
| 型號： | ARM610 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲器管理單元）) |
| 中文描述： | 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲器管理單元）） |
| 文件頁數(shù)： | 100/174頁 |
| 文件大?。?/td> | 694K |
| 代理商： | ARM610 |
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Write Buffer (WB)
ARM610 Data Sheet
7-2
7.1
Introduction
The ARM610 write buffer is provided to improve system performance. It can buffer up
to eight words of data, and two independent addresses. It may be enabled or disabled
via the W bit (bit 3) in the ARM610 Control Register and the buffer is disabled and
flushed on reset. The operation of the write buffer is further controlled by one bit, B, or
Bufferable, which is stored in the Memory Management Page Tables. For this reason,
in order to use the write buffer, the MMU must be enabled. The two functions may
however be enabled simultaneously, with a single write to the Control Register. For a
write to use the write buffer, both the W bit in the Control Register, and the B bit in the
corresponding page table must be set.
7.2
Bufferable Bit
This bit controls whether a write operation may or may not use the write buffer.
Typically main memory will be bufferable and I/O space unbufferable. The Bufferable
bit can be configured for both pages and sections.
7.3
Write Buffer Operation
When the CPU performs a write operation, the translation entry for that address is
inspected and the state of the B bit determines the subsequent action. If the write
buffer is disabled via the ARM610 Control Register, bufferable writes are treated in the
same way as unbuffered writes.
7.3.1 Bufferable write
If the write buffer is enabled and the processor performs a write to a bufferable area,
the data is placed in the write buffer at
FCLK
execution. The write buffer then performs the external write in parallel. If however the
write buffer is full (either because there are already eight words of data in the buffer,
or because there is no slot for the new address) then the processor is stalled until there
is sufficient space in the buffer.
speeds and the CPU continues
7.3.2 Unbufferable writes
If the write buffer is disabled or the CPU performs a write to an unbufferable area, the
processor is stalled until the write buffer empties and the write completes externally,
which may require synchronisation and several external clock cycles.
7.3.3 Read-lock-write
The write phase of a read-lock-write sequence is treated as an Unbuffered write, even
if it is marked as buffered.
Note
A single write requires one address slot and one data slot in the write buffer; a
sequential write of n words requires one address slot and n data slots. The total of 8
data slots in the buffer may be used as required. So for instance there could be one
non-sequential write and one sequential write of seven words in the buffer, and the
processor could continue as normal: a third write or an eighth word in the second write
would stall the processor until the first write had completed.
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