參數(shù)資料
型號(hào)： ARM610
廠商： Mitel Networks Corporation
英文描述： General Purpose 32-Bit Microprocessor with 4kByte Cache,Write Buffer and Memory Management Unit(通用32位微處理器（帶4K字節(jié)緩存，寫緩沖器和存儲(chǔ)器管理單元）)
中文描述： 通用32位微處理器4KB的高速緩存，寫緩沖器和存儲(chǔ)器管理單元（通用32位微處理器（帶4K的字節(jié)緩存，寫緩沖器和存儲(chǔ)器管理單元））
文件頁數(shù)： 129/174頁
文件大?。?/td> 694K
代理商： ARM610
Bus interface
ARM610 Data Sheet
10-5
10.8 Memory Access Types
ARM610 performs many different bus accesses, and all are constructed out of
combinations of nonsequential and sequential accesses. There may be any number of
idle cycles between two other memory accesses. If a memory access is followed by
an idle period on the bus (as opposed to another nonsequential access), the address,
and the signal
nRW
and
nBW
, will remain at their previous value in order to avoid
unnecessary bus transitions.
The accesses performed by an ARM610 are:
Unbuffered Write
See
·
10.8.1 Unbuffered Writes / Uncacheable Reads
Buffered Write
See
·
10.8.2 Buffered Write
Linefetch
See
·
10.8.3 Linefetch
Level 1 translation fetch
See
·
10.8.4 Translation Fetches
Level 2 translation fetch
See
·
10.8.4 Translation Fetches
Read-Lock-Write sequence
See
·
10.8.5 Read - Lock - Write
10.8.1 Unbuffered Writes / Uncacheable Reads
These are the most basic access types. Apart from the difference between read and
write, they are the same. Each may consist of a single (LDR/STR) or multiple (LDM/
STM) access. A multiple access consists of a nonsequential access followed by a
sequential access. These cycles always reflect the type of the instruction requesting
the cycle (ie. read/write, byte/word).
10.8.2 Buffered Write
The external bus cycle of a buffered write is identical to and indistinguishable from the
bus cycle of an unbuffered write. These cycles always reflect the type (byte/word) of
the instruction requesting the cycle. If several write accesses are stored concurrently
within the write buffer, each access on the bus will start with a nonsequential access.
10.8.3 Linefetch
This appears on the bus as a nonsequential access followed by three sequential
accesses. Linefetch accesses always start on a quad-word boundary, and are always
word accesses. So if the instruction which caused the linefetch was a byte load
instruction (ie. LDRB), the linefetch access will be a word access on the bus.
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