參數(shù)資料
型號: 84220
廠商: LSI Corporation
英文描述: Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device (Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications)(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器(高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器))
中文描述: 四100BaseTX/100BaseFX/10BaseT物理層裝置(高度集成的以太網(wǎng)收發(fā)器,雙絞線和光纖以太網(wǎng)的應(yīng)用)(四通道100BaseTX/100BaseFX/10BaseT物理層處理器(高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器) )
文件頁數(shù): 91/92頁
文件大?。?/td> 1401K
代理商: 84220
91
MD400177/B
84220
Revision History
2/15/99
2/15/99 Document changed to MD400177/B
Page 7, Pin Description cont’d
- Pin # 110, I/O, Pulldown has been removed.
Page 36, Table 10. MI Serial Port Register Map
- Bit 4.10 and 5.10 have been changed from 0 to Pause.
Page 41, Table 15 Register 4 - AutoNegotiation Advertisement Register Definition
- Bit 4.10 has been changed from 0 to Pause
- Row 4.10 Pause has been added.
Page 42, Table 16 Register 5 - AutoNegotiation Remote Capability Definition
- Bit 5.10 has been changed from 0 to Pause
- Row 5.10 Pause has been added.
Page 49, Figure 12. Typical Switching Hub Port Schematic Using the 88220/88221 in Twisted Pair Mode
- 16x Optional has been added to LED[3:0]_[7:0] Lead
- LED[3:0]_[7:0], has been changed to LED[3:0]_[7:0]
- TXD3_3, RXD3_3 have been changed to 3_3, 2_3, 1_3, 0_3, respectively.
- TXD2_3, RXD2_3 have been changed to 3_2, 2_2, 1_2, 0_2, respectively.
- TXD1_3, RXD1_3 have been changed to 3_1, 2_1, 1_1, 0_1, respectively.
- TXD0_3, RXD0_3 have been changed to 3_0, 2_0, 1_0, 0_0, respectively.
- RJ45 Leads have been changed from 1, 2, 5, 6, 7, 8, 9, 0 to 1, 2, 4, 5, 7, 8, 3, 6.
- Unmarked resistor is now 75 and is connected to first capacitor.
Page 50. Figure 13. Typical Switching Hub Port Schematic Using the 84220 in FX Mode with 3.3V Transceivers
- LED[3:0]_[7:0], has been changed to LED[3:0]_[7:0]
- TXD3_3, RXD3_3 have been changed to 3_3, 2_3, 1_3, 0_3, respectively.
- TXD2_3, RXD2_3 have been changed to 3_2, 2_2, 1_2, 0_2, respectively.
- TXD1_3, RXD1_3 have been changed to 3_1, 2_1, 1_1, 0_1, respectively.
- TXD0_3, RXD0_3 have been changed to 3_0, 2_0, 1_0, 0_0, respectively.
- 16x Optional has been added to LED[3:0]_[7:0] Lead
Page 51, 4.2.2 Receive Interface
- Paragraph #3 Copy changed ...that a 0.1uF capacitor be placed between the center of the series resistor string and
GND in order .. . to ...that a 0.01uF capacitor be placed between the center of the series resistor string and VDD
in order
Page 55 , 4.10.1 General
- Paragraph #4, reference to Section 4.7.4 has been deleted.
Page 66, Receive Timing Charateristics
- t
37
, LIMIT (MIN) has been cahnged from -4 to 2, LIMIT (MAX) has been changed from 2 to 6.
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