參數(shù)資料
型號(hào)： 84220
廠商： LSI Corporation
英文描述： Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
中文描述： 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ）
文件頁(yè)數(shù)： 27/92頁(yè)
文件大?。?/td> 1401K
代理商： 84220
MD400177/B
84220
27
2.16.3 Autopolarity Disable
The autopolarity feature can be disabled by setting the
autopolarity disable bit in the MI serial port Global
Configuration register.
2.17 FULL DUPLEX MODE
2.17.1 100 Mbps
Full Duplex mode allows transmission and reception to
occur simultaneously. When Full Duplex mode is enabled,
collision is disabled, and internal TXEN to CRS loopback
is disabled.
The device can be either forced into Half or Full Duplex
mode, or the device can detect either Half or Full Duplex
capability from a remote device and automatically place
itself in the correct mode.
Each channel can be forced into the Full or Half Duplex
modes by either setting the duplex bit in the MI serial port
Control register or asserting the DPLX pin for the
corresponding channel with AutoNegotiation disabled.
The device can automatically configure itself for Full or
Half Duplex modes by using the AutoNegotiation algorithm
to advertise and detect Full and Half Duplex capabilities to
and from a remote terminal. For detailed information, refer
to the LINK INTEGRITY & AUTONEGOTIATION Section.
2.17.2 10 Mbps
Full Duplex in 10 Mbps mode is identical to the 100 Mbps
mode.
2.17.3 Full Duplex Indication
Full Duplex detect activity can be monitored through the
duplex detect bit in the MI serial port Channel Status
Output register.
Full Duplex detect activity also appears on the LED1 pin
by default. The LED outputs can be programmed to
indicate four specific sets of events, by appropriately
setting the LED definition bits in the MI serial port Global
Configuration register. The LED DRIVERS Section
describes the programmable LED definition bit settings.
Note that Full Duplex detection appears on the LED1 pin
in each of the four sets of events. The LED1 pin is
asserted low when the device is configured for Full Duplex
operation.
2.18 10/100 MBPS SELECTION
2.18.1 General
The device can be forced into either the 100 or 10 Mbps
mode, or the device can detect 100 or 10 Mbps
capability from a remote device and automatically place
itself in the correct mode.
The device can be forced into either the 100 or 10 Mbps
mode by either setting the speed select bit in the MI serial
port Control register or by setting the SPEED pin with
AutoNegotiation disabled. Both the speed select bit and
SPEED pin need to be set to the same speed (10 or 100)
for the device to be properly configured. The speed select
bit and SPEED pin are ignored if AutoNegotiation is
enabled.
The device can automatically configure itself for 100 or 10
Mbps mode by using the AutoNegotiation algorithm to
advertise and detect 100 and 10 Mbps capabilities to and
from a remote device. Refer to the LINK INTEGRITY &
AUTONEGOTIATION Section for more details on
AutoNegotiation.
2.18.2 10/100 MBPS Indication
The device speed (100/10 Mbps) can be monitored
through the speed bit in the MI serial port Channel Status
Output register.
The device speed can also be programmed to appear on
the LED0 pin, by appropriately setting the LED definition
bits in the MI serial port Global Configuration register. The
LED DRIVERS Section describes the programmable LED
definition bit settings. When the LED0 pin is programmed
to be a speed detect output, the pin is asserted low when
the device is configured for 100 Mbps operation.
2.19 LOOPBACK
2.19.1 Internal CRS Loopback
TXEN is internally looped back onto CRS during every
transmit packet. This internal CRS loopback is disabled
during collision, in Full Duplex mode, in Link Fail State,
and in RMII mode. In 10 Mbps mode, internal CRS
loopback is also disabled when jabber is detected.
相關(guān)PDF資料
PDF描述
84221 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99
84221 Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
84301 84301 4-Port Fast Ethernet Controller manual 3/98
84301 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
84717000 MINIATURNAEHERUNGSSCHALTER 4MM GLATT PNP
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