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| 型號： | 84220 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 31/92頁 |
| 文件大小： | 1401K |
| 代理商： | 84220 |
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MD400177/B
84220
31
2.26.3 Multiple Register Access
Multiple registers can be accessed on a single MI serial
port access cycle with the multiple register access
feature. The multiple register access feature can be
enabled by setting the multiple register access enable bit
in the Global Configuration Register for all channels.
When multiple register access is enabled, all registers
can be accessed on a single MI serial port access cycle
by setting the register address to 11111 during the first 16
MDC clock cycles. There is no actual register residing in
register address location 11111.
When the register address is set to 11111, all eleven
registers are accessed for all four channels on the 704
rising edges of MDC (4 x 11 x 16) that occur after the first
16 MDC clock cycles of the MI serial port access cycle.
The registers are accessed in numerical order from 0 to
20 for each channel and from channel 0 to 3. After all 720
MDC clocks have been completed, all the registers have
been read/written, and the serial shift process is halted,
data is latched into the device, and MDIO goes into high
impedance state. Another serial shift cycle cannot be
initiated until the idle condition (at least 32 continuous 1's)
is detected.
2.26.4 Bit Types
Since the serial port is bidirectional, there are many types
of bits. The bit type definitions are summarized in Table 8.
Write bits (W) are inputs during a write cycle and are high
impedance during a read cycle. Read bits (R) are outputs
during a read cycle and high impedance during a write
cycle. Read/Write bits (R/W) are actually write bits that
can be read out during a read cycle. R/WSC bits are R/W
bits that are self clearing after a set period of time or after
a specific event has completed. R/LL bits are read bits
that latch themselves when they go low, and they stay
latched low until read. After they are read, they are reset
high. R/LH bits are the same as R/LL bits, except that
they latch high. R/LT are read bits that latch themselves
whenever they make a transition or change value, and
they stay latched until they are read. After R/LT bits are
read, they are updated to their current value. The R/LT
bits can also be programmed to assert the interrupt
function as described in the Interrupt section.
Table 8. MI Register Bit Type Definition
2.26.5 Frame Structure
The structure of the serial port frame is shown in Table 9
and a timing diagram is shown in Figure 10. Each serial
port access cycle consists of 32 bits (or 720 bits if multiple
register access is enabled and REGAD[4:0]=11111),
Symbol
Name
Definition
Write Cycle
Input
Read Cycle
No Operation, Hi
Z
W
Write
R
Read
No Operation, Hi
Z
Output
R/W
Read/Write
Input
Output
R/
WSC
Read/
Write
Self Clear-
ing
Input
Clears Itself
After Opera-
tion Com-
pleted
Output
R/LL
Read/
Latching
Low
No Operation,
Hi Z
Output
When Bit Goes
Low,
Bit Latched.
When Bit Is
Read, Bit
Updated.
R/LH
Read/
Latching
High
No Operation,
Hi Z
Output
When Bit Goes
High,
Bit Latched.
When Bit Is
Read, Bit
Updated.
R/LT Read/
Latching
on Transi-
tion
No Operation,
Hi Z
Output
When Bit
Transitions,
Bit Latched And
Interrupt Set
When Bit Is
Read, Interrupt
Cleared And Bit
Updated.
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