參數(shù)資料
型號： 84220
廠商： LSI Corporation
英文描述： Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
中文描述： 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ）
文件頁數(shù)： 62/92頁
文件大?。?/td> 1401K
代理商： 84220
MD400177/B
84220
62
AC Test Timing Conditions
Unless otherwise noted, all test conditions are as follows:
1. T
A
= 0 to +70
C
2. V
DD
= 3.3 V +5%
3. 25 MHz +0.01%
4. REXT = 10K +1%, no load
5. Input conditions:
All Inputs:
6. Output Loading
TPOP/N:
MDINT:
All Other Digital Outputs:
7. Measurement Points:
TPOP/N, TPIP/N:
All other inputs and outputs:
o
tr,tf <= 10 nS, 20-80%
Same as Figure 12 or Equivalent, 10 pF
1K Pullup, 50 pF
25 pF
0 V During Data, +0.3 V at start/end of packet
1.4 V
5.7 Clock Timing Characteristics
Refer To Figure 16 For Timing Diagram
LIMIT
SYM
t
1
PARAMETER
CLKIN Period
MIN
39.996
19.996
16
7
16
7
TYP
40
20
MAX
40.004
20.002
UNIT
nS
nS
nS
nS
nS
nS
nS
CONDITIONS
MII
RMII
MII
RMII
MII
RMII
100 Mbps, MII
t
2
CLKIN High Time
t
3
CLKIN Low Time
t
4
CLKIN to TXCLK Delay
10
20
nS
10 Mbps, MII
TXCLK
(100 MB)
TXCLK
(10 MB)
t4
t4
t4
CLKIN
t1
t2
t3
Figure 16. Output Timing
相關(guān)PDF資料
PDF描述
84221 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99
84221 Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
84301 84301 4-Port Fast Ethernet Controller manual 3/98
84301 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
84717000 MINIATURNAEHERUNGSSCHALTER 4MM GLATT PNP
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