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參數(shù)資料
| 型號： | 84220 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 14/92頁 |
| 文件大?。?/td> | 1401K |
| 代理商： | 84220 |
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14
MD400177/B
84220
2.2.5 RMII - 10 Mbps
10 Mbps RMII operation is identical to 100 Mbps RMII
operation, except:
The CLKIN frequency remains at 50 Mhz (same as 100
Mbps operation).
Each data di-bit must be input on TXD[1:0] for ten
consecutive CLKIN cycles.
Each data di-bit will be output on RXD[1:0] for ten
consecutive CLKIN cycles.
2.2.6 FBI - 100 Mbps
The Five Bit Interface (FBI), or Symbol Interface, is a five
bit wide interface produced when the 4B5B encoder/
decoder is bypassed. The FBI is primarily used for
repeaters or Ethernet controllers that have integrated
encoder/decoders.
The FBI is identical to the MII, except:
The FBI data path is five bits wide, not nibble wide like
the MII.
TXER pin is changed to be the fifth transmit data bit,
TXD4.
RXER pin is changed to be the fifth receive data bit,
RXD4.
CRS is asserted as long as the device is in the Link
Pass state (CRS no longer asserted/deasserted at
beginning/end of packet).
COL is not valid.
RXDV is not valid.
TXEN is ignored.
2.2.7 FBI - 10 Mbps
The FBI is not available in 10 Mbps mode.
2.2.8 Selection of MII, RMII, or FBI
MII is the default interface to the MAC controller. RMII is
selected by asserting the RMII_EN pin, a global control.
The FBI is automatically enabled when the 4B5B encoder/
decoder is bypassed. Bypassing the encoder/decoder
passes the 5B symbols between the receiver/transmitter
directly to the FBI without any alteration or substitutions.
The 4B5B encoder/decoder can be bypassed by setting
the bypass encoder bit in the MI serial port Channel
Configuration register.
When the FBI is enabled, it may also be desirable to
bypass the scrambler/descrambler and disable the
internal CRS loopback function. The scrambler/
descrambler can be bypassed by setting the bypass
scrambler bit in the MI serial port Channel Configuration
register. The internal CRS loopback can be disabled by
setting the TXEN to CRS loopback disable bit in the MI
serial port Channel Configuration register.
2.2.9 MII Disable
The MII and FBI inputs and outputs can be disabled by
setting the MII disable bit in the MI serial port Control
register. When the MII is disabled, the inputs are ignored,
the outputs are placed in high impedance state, and the
TP output is high impedance.
2.2.10 TXEN to CRS Loopback Disable
The internal TXEN to CRS loopback can be disabled by
appropriately setting the TXEN to CRS loopback disable
bit in the MI serial port Channel Configuration register.
TXEN to CRS loopback is disabled in RMII mode.
2.3 ENCODER
2.3.1 4B5B Encoder - 100 Mbps
100BaseTX and 100BaseFX require that the data be
4B5B encoded. 4B5B coding converts the 4 bit data
nibbles into 5 bit data words. The mapping of the 4B
nibbles to the 5B code words is specified in IEEE 802.3
and shown in Table 1. The 4B5B encoder on the 84220
takes 4B nibbles from the controller interface, converts
them into 5B words according to, Table 1, and sends the
5B words to the scrambler. The 4B5B encoder also
substitutes the first eight bits of the preamble with the
SSD delimiters (/J/K/ symbols) and adds an ESD
delimiter (/T/R/ symbols) to the end of each packet, as
defined in IEEE 802.3 and shown in Figure 2. The 4B5B
encoder also fills the period between packets, called the
idle period, with a continuous stream of idle symbols, as
shown in Figure 2.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 84221 | 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99 |
| 84221 | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 84301 | 84301 4-Port Fast Ethernet Controller manual 3/98 |
| 84301 | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 84717000 | MINIATURNAEHERUNGSSCHALTER 4MM GLATT PNP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 8422002AGI | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI - Rail/Tube |
| 8422002AGI-01 | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01 - Rail/Tube |
| 8422002AGI-01LF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER |
| 8422002AGI-01LFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER |
| 8422002AGI-01T | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01T - Tape and Reel |
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