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參數(shù)資料
| 型號： | 84220 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 17/92頁 |
| 文件大?。?/td> | 1401K |
| 代理商： | 84220 |
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MD400177/B
84220
17
If the descrambler is in the unsynchronized state, the
descrambler loss of synchronization detect bit is set in the
MI serial port Channel Status Output register to indicate
this condition. Once this bit is set, then it will stay set until
the descrambler achieves synchronization.
A descrambler is not used for FX operation.
2.7.2 10 Mbps
A descrambler is not used in 10 Mbps mode.
2.7.3 Descrambler Bypass
The descrambler can be bypassed by setting the bypass
scrambler/descrambler bit in the MI serial port Channel
Configuration register. When this bit is set, the data
bypasses the descrambler and goes directly from the TP
receiver to the 4B5B decoder.
2.8 TWISTED PAIR TRANSMITTER
2.8.1 100 Mbps
The TP transmitter consists of an MLT3 encoder,
waveform generator and line driver.
The MLT3 encoder converts the NRZI data from the
scrambler into a three level code required by IEEE 802.3.
MLT3 coding uses three levels and converts 1's to
transitions between the three levels, and converts 0's to no
transitions or changes in level.
The purpose of the waveform generator is to shape the
transmit output pulse. The waveform generator takes the
MLT3 three level encoded waveform and uses an array of
switched current sources to control the shape of the
twisted pair output signal in order to meet IEEE 802.3
requirements. The output of the switched current sources
then goes through a low pass filter in order to "smooth"
the output and remove any high frequency components.
In this way, the waveform generator preshapes the output
waveform transmitted onto the twisted pair cable to meet
the pulse template requirements outlined in IEEE 802.3.
The waveform generater eliminates the need for any
external filters on the TP transmit output. The line driver
converts the shaped and smoothed waveform to a current
output that can drive 100 meters of category 5 unshielded
twisted pair cable or 150 ohm shielded twisted pair cable.
2.8.2 10 Mbps
The TP transmitter operation in 10 Mbps mode is much
different than the 100 Mbps transmitter. Even so, the
transmitter still consists of a waveform generator and line
driver.
The purpose of the waveform generator is to shape the
output transmit pulse. The waveform generator consists
of a ROM, DAC, clock generator, and filter. The DAC
generates a stair-stepped representation of the desired
output waveform. The stairstepped DAC output then
goes through a low pass filter in order to "smooth" the
DAC output and remove any high frequency components.
The DAC values are determined from the ROM output; the
ROM outputs are chosen to shape the pulse to the
desired template and are clocked into the DAC at high
speed by the clock generator. In this way, the waveform
generator preshapes the output waveform to be
transmitted onto the twisted pair cable to meet the pulse
template requirements outlined in IEEE 802.3 Clause 14
and also shown in Figure 4. The waveshaper replaces and
eliminates external filters on the TP transmit output.
The line driver converts the shaped and smoothed
waveform to a current output that can drive 100 meters of
category 3/4/5 100 Ohm unshielded twisted pair cable or
150 Ohm shielded twisted pair cable, without any external
filters. During the idle period, no output signal is
transmitted on the TP outputs (except link pulse).
2.8.3 Transmit Level Adjust
The transmit output current level is derived from an
internal reference voltage and the external resistor on
REXT pin.
The transmit level (100 Base TX, and 10 Base T) can be
adjusted with either the external resistor on the REXT pin,
or the four transmit level adjust bits in the MI serial port
Global Configuration register as shown in Table 2. The
adjustment range is -14% to +16% in 2% steps.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 84221 | 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99 |
| 84221 | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 84301 | 84301 4-Port Fast Ethernet Controller manual 3/98 |
| 84301 | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 84717000 | MINIATURNAEHERUNGSSCHALTER 4MM GLATT PNP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| 8422002AGI | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI - Rail/Tube |
| 8422002AGI-01 | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01 - Rail/Tube |
| 8422002AGI-01LF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER |
| 8422002AGI-01LFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER |
| 8422002AGI-01T | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01T - Tape and Reel |
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