參數(shù)資料
型號： 84220
廠商： LSI Corporation
英文描述： Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
中文描述： 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ）
文件頁數(shù)： 54/92頁
文件大?。?/td> 1401K
代理商： 84220
54
MD400177/B
84220
For normal MII operation the RMII_EN pin should be tied
to GND. Refer to the RMII description in Section 2 for
details of the interface operation.
4.7.2 Clocks
Standard Ethernet controllers with an MII use TXCLK to
clock data in on inputs TXD[3:0]. TXCLK is specified in
IEEE 802.3 and on the 84220 to be an output. The 84220
requires a 25 MHz reference frequency in MII mode, and
50 MHz in RMII mode. This reference frequency must be
applied to the CLKIN pin. CLKIN generates TXCLK inside
the 84220; thus, data can be clocked into the 84220 on
the rising edge of output clock TXCLK or on the rising
edge of input clock CLKIN.
If a nonstandard controller is used to interface to the
84220, or in Repeater Applications, there may be a need
to clock TXD[3:0] into the 84220 on the rising edge
CLKIN. Where CLKIN is used as the input clock, TXCLK
can be left open or used for another purpose.
4.7.3 MII Disable
The MII outputs can be placed in the high impedance
state and inputs disabled by setting the MII disable bit in
the MI serial port Control register. When this bit is set to
the disable state, the TP and FX outputs are both
disabled and transmission is inhibited. The default value
of this bit when the device powers up or is reset is
dependent on the device address. If the device address
latched into PHYAD[4:0] at reset is 11111, it is assumed
that the device is being used in applications where there
maybe more than one device sharing the MII bus, like
external PHY’s or adapter cards, so the device powers up
with the MII interface disabled. If the device address
latched into PHYAD[4:0] at reset is not 11111, it is
assumed that the device is being used in an application
where it is the only device on the MII bus, like hubs, so the
device powers up with the MII interface enabled.
4.8 FBI CONTROLLER INTERFACE
The FBI (Five Bit Interface) controller interface has the
same characteristics of the MII except that the data path
is ive bits wide, instead of 4 bits wide per the MII. The ive
bit wide data path is automatically enabled when the
4B5B encoder is bypassed. Because of this encoder/
decoder bypass, the FBI is used primarily for repeaters or
other applications where the PHY encoding/decoding
function is not needed. For more details about the FBI,
see the Non-MII Based Repeaters Section.
4.9 REPEATER APPLICATIONS
4.9.1 MII Based Repeaters
The 84220 can be used as the physical interface for MII
based repeaters by using the standard MII/RMII as the
interface to the repeater core.
For most repeaters, it is necessary to disable the internal
CRS loopback. This can be done be setting the TXEN to
CRS loopback disable bit in the MI serial port Channel
Configuration register.
For some particular types of repeaters, it may be
desirable to either enable or disable AutoNegotiation,
force Half Duplex operation, and enable either 100 Mbps
or 10 Mbps operation. All of these modes can be
configured by setting the appropriate bits in the MI serial
port Control register.
The 84220 also has a REPEATER pin and a repeater
mode select bit which will automatically configure the
device for one common type of repeater application.
When the REPEATER pin is asserted:
TXEN to CRS loopback is disabled
AutoNegotiation is disabled
Half Duplex operation is selected
100 Mbps operation is selected.
The Hardware configuration pins (ANEG, SPEED_[3:0],
DPLX_[3:0] are disabled while the Repeater input pin is
asserted.
4.9.2 Non-MII Based Repeaters
The FBI interface available on the 84220 can be used to
connect to non-MII based repeaters that employ the
popular five bit wide interface.
Since the FBI is a 5 bit wide interface, it requires that the
4B5B encoder/decoder be bypassed. The FBI is
automatically selected on the 84220 when the 4B5B
encoder/decoder is bypassed. The 4B5B encoder/
decoder can be bypassed by setting the bypass encoder/
decoder select bit in the MI serial port Channel
Configuration register.
For most repeaters, it is necessary to disable the internal
CRS loopback. This can be done by setting the TXEN to
CRS loopback disable bit in the MI serial port
Configuration 1 register.
相關PDF資料
PDF描述
84221 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99
84221 Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
84301 84301 4-Port Fast Ethernet Controller manual 3/98
84301 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
84717000 MINIATURNAEHERUNGSSCHALTER 4MM GLATT PNP
相關代理商/技術參數(shù)
參數(shù)描述
8422002AGI 制造商:Integrated Device Technology Inc 功能描述:8422002AGI - Rail/Tube
8422002AGI-01 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01 - Rail/Tube
8422002AGI-01LF 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
8422002AGI-01LFT 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER
8422002AGI-01T 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01T - Tape and Reel
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