參數(shù)資料
型號(hào)： 84220
廠商： LSI Corporation
英文描述： Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
中文描述： 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ）
文件頁數(shù)： 16/92頁
文件大?。?/td> 1401K
代理商： 84220
16
MD400177/B
84220
2.4.3 Decoder Bypass
The 4B5B decoder can be bypassed by setting the bypass
encoder/decoder bit in the MI serial port Channel
Configuration register. When this bit is set to bypass the
encoder/decoder:
5B code words are passed directly to the controller
interface from the descrambler without any alterations.
CRS is asserted whenever the device is in the Link Pass
state.
2.5 CLOCK AND DATA RECOVERY
2.5.1 Clock Recovery - 100 Mbps
Clock recovery is done with a PLL. If there is no valid data
present on the receive inputs, the PLL is locked to the 25
MHz TXCLK. When valid data is detected on the receive
inputs with the squelch circuit and when the adaptive
equalizer has settled, the PLL input is switched to the
incoming data stream. The PLL then recovers a clock by
locking onto the transitions of the incoming signal. The
recovered clock frequency is a 25 MHz nibble clock, and
that clock is output as the controller interface signal
RXCLK.
For FX operation, when the SD pin is asserted, the PLL
input is switched to the incoming data on the input.
2.5.2 Data Recovery - 100 Mbps
Data recovery is performed by latching in data from the
receive inputs with the recovered clock extracted by the
PLL. The data is then converted from a single bit stream
into a nibble widedone by latching in valid data from the
receiver with the recovered clock extracted by the PLL.
The data is then converted from a a single bit stream into
a nibble wide data word.
2.5.3 Clock Recovery - 10 Mbps
The clock recovery process for 10 Mbps mode is identical
to the 100 Mbps mode, except:
The recovered clock frequency is a 2.5 MHz nibble
clock.
The PLL is switched from TXCLK to the TP input when
the squelch indicates valid data.
The PLL locks onto the preamble signal in less than 12
transitions (bit times).
Some of the preamble data symbols are lost while the
PLL is locking onto the preamble, however, the data
receiver block recovers enough preamble symbols to
pass at least 6 nibbles of preamble to the controller
interface as shown in Figure 3.
2.5.4 Data Recovery
The data recovery process for 10 Mbps mode is identical
to the 100 Mbps mode, except, the recovered clock
frequency is a 2.5 MHz nibble clock. As mentioned in the
Manchester Decoder section, the data recovery process
inherently performs decoding of Manchester encoded
data from the TP inputs.
2.6 SCRAMBLER
2.6.1 100 Mbps
100BaseTX requires scrambling to reduce the radiated
emmisions on the twisted pair. The 84220 scrambler
takes the encoded data from the 4B5B encoder,
scrambles it per the IEEE 802.3 specifications, and sends
it to the TP transmitter. The scrambler circuitry of the
84220 is designed so that none of the individual scrambler
sections on-chip will be synchronous with the others to
minimize EMI issues.
2.6.2 10 Mbps
A scrambler is not used in 10 Mbps mode.
2.6.3 Scrambler Bypass
The scrambler can be bypassed by setting the bypass
scrambler/descrambler bit in the MI serial port Channel
Configuration register. When this bit is set, the 5B data
bypasses the scrambler and goes directly from the 4B5B
encoder to the twisted pair transmitter.
2.7 DESCRAMBLER
2.7.1 100 Mbps
The 84220 descrambler takes the scrambled data from
the data recovery block, descrambles it per the IEEE
802.3 specifications, aligns the data on the correct 5B
word boundaries, and sends it to the 4B5B decoder.
The algorithm for synchronization of the descrambler is
the same as the algorithm outlined in the IEEE 802.3
specification. Once the descrambler is synchronized, it
will maintain synchronization as long as enough
descrambled idle pattern 1’s are detected within a given
interval. To stay in synchronization, the descrambler
needs to detect at least 25 consecutive descrambled idle
pattern 1’s in a 1 mS interval. If 25 consecutive
descrambled idle pattern 1’s are not detected within the 1
mS interval, the descrambler goes out of synchronization
and restarts the synchronization process.
相關(guān)PDF資料
PDF描述
84221 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99
84221 Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
84301 84301 4-Port Fast Ethernet Controller manual 3/98
84301 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
84717000 MINIATURNAEHERUNGSSCHALTER 4MM GLATT PNP
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8422002AGI-01T 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01T - Tape and Reel
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