參數(shù)資料
型號(hào)： 84220
廠商： LSI Corporation
英文描述： Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
中文描述： 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ）
文件頁(yè)數(shù)： 32/92頁(yè)
文件大小： 1401K
代理商： 84220
32
MD400177/B
84220
The structure and bit definition of the Global Configuration
Register is shown in Table 17. This register is common for
all four channels. It stores various configuration inputs.
The structure and bit definition of the Channel
Configuration Register is shown in Table 18. This register
stores various configuration inputs unique to each
channel.
The structure and bit definition of the Channel Status
Output Register is shown in Table 19. This register
contains output status information from each channel.
The structure and bit definition of the Global Interrupt
Mask Register is shown in Table 20. This register is
common for all four channels. Bit 7 is the interrupt
indication. The 7 least significant bits are the Mask bits for
the R/LT status bits in the Channel Status Output Register.
Register 20 in Table 21 is reserved for factory use only. All
bits must be set to the pre-set default states shown for
normal operation.
2.26.7 Interrupt
The 84220 has hardware and software interrupt capability.
The interrupt is triggered by certain output status bits (also
referred to as interrupt bits) in the serial port.
Bits [6:0] in Channel Status Output Register are interrupt
bits if they are not masked out with the mask bits in the
Global Interrupt Mask register. These interrupt bits are R/
LT as indicated previously. That is, they are read bits that
latch on transition.
Interrupt bits automatically latch themselves into their
register locations and assert the interrupt indication when
they change state. Interrupt bits stay latched until they are
read. When all interrupt bits are read, the interrupt
indication is deasserted and the interrupt bits that caused
the interrupt to happen are updated to their current value.
Each interrupt bit can be individually masked and
subsequently be removed as an interrupt bit by setting the
appropriate mask register bits in the lower half of the
Global Configuration Register.
Interrupt indication is done in three ways:
(1) MDINT pin
The MDINT pin is an active low interrupt output
indication.
exclusive of idle. The first 16 bits of the serial port cycle
are always write bits and are used for addressing. The last
16/704 bits are from one/all of the 4 x 11 data registers.
The first 2 bits in Table 9 and Figure 10 are start bits and
need to be written as a 01 for the serial port cycle to
continue. The next 2 bits are read and write bits which
determine whether the accessed data register bits will be
read or write. The next 5 bits are device addresses. The 3
most significant bits must match the values on pins
PHYAD[4:2] and the 2 least significant bits select one of
four channels for access. The next 5 bits are register
address select bits which select one of the eleven
registers for access. The next 2 bits are turnaround bits
which are not an actual register bits but extra time to
switch MDIO from write to read if necessary. The final 16
bits of the MI serial port cycle (or 704 bits if multiple
register access is enabled and REGAD[4:0]=11111) come
from the specific data register designated by the register
address bits REGAD[4:0].
2.26.6 Register Structure
The 84220 has eleven 16 bit registers for each channel. All
eleven registers are available for setting configuration
inputs and reading status outputs. A map of the registers
is shown in Table 10. The eleven registers consist of six
registers that are defined by IEEE 802.3 specifications
(Registers 0-5) and five registers that are unique to the
84220 (Registers 16-20).
The structure and bit definition of the Control Register is
shown in Table 11. This register stores various
configuration inputs and its bit definition complies with the
IEEE 802.3 specifications.
The structure and bit definition of the Status Register is
shown in Table 12. This register contains device
capabilities and status output information and its bit
definition complies with the IEEE 802.3 specifications.
The structure and bit definition of the PHY ID Register 1
and PHY ID Register 2 is shown in Table 13 and Table 14,
respectively. These registers contain an identification code
unique to the 84220 and their bit definition complies with
the IEEE 802.3 specifications.
The structure and bit definition of the Auto Negotiation
Advertisement and Auto Negotiation Remote End
Capability registers is shown in Table 15 and Table 16,
respectively. These registers are used by the Auto
Negotiation algorithm and their bit definition complies with
the IEEE 802.3 specifications.
相關(guān)PDF資料
PDF描述
84221 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99
84221 Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
84301 84301 4-Port Fast Ethernet Controller manual 3/98
84301 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
84717000 MINIATURNAEHERUNGSSCHALTER 4MM GLATT PNP
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