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參數(shù)資料
| 型號(hào)： | 84220 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 51/92頁 |
| 文件大?。?/td> | 1401K |
| 代理商： | 84220 |
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MD400177/B
84220
51
Table 24. TP Transformer Sources
4.2.2 Receive Interface
Receive data is typically transformer coupled into the
receive inputs on TPIP/N and terminated with an
external resistor as shown in Figure 12.
The transformer for the receiver is recommended to have
a winding ration of 1:1, as shown in Figure 12. The
specifications for such a transformer are shown in Table
23. Sources for the transformer are listed in Table 24.
The receive input needs to be terminated with the correct
termination impedance to meet the input impedance and
return loss requirements of IEEE 802.3. In addition, the
receive TP inputs need to be attenuated. It is
recommended that both the termination and attenuation
be accomplished by placing four external resistors in
series across the TPIP/N inputs as shown in Figure 12.
The resistors should be 25%/25%/25%/25% of the total
series resistance, and the total series resistance should
be equal to the characteristic impedance of the cable
(100 ohms for UTP 150 Ohms for STP). For 100 Ohm
twisted pair the resistor string values should be 25 Ohms
each (1%). It is also recommended that a 0.01uF
capacitor be placed between the center of the series
resistor string and VDD in order to provide an AC ground
for attenuating common mode signal at the input. This
capacitor is also shown in Figure 12.
To minimize common mode input noise and to aid in
meeting susceptibility requirements, it may be necessary
to add a common mode choke on the receive input as
well as add common mode bundle termination. The
transformers listed in Table 28 on page 48 all contain
common mode chokes on both the transmit and receive
sides, as shown in Figure 12. Common mode bundle
termination is achieved by tying the receive secondary
center tap and the unused pairs in the RJ45 to chassis
ground through 75 ohm resistors and a 0.01 uF capacitor,
as shown in Figure 12.
In order to minimize noise pickup into the receive path in
a system or on a PCB, the loading on TPIP/N should be
minimized and both inputs should be loaded equally.
4.3 TP TRANSMIT OUTPUT CURRENT SET
The TPOP/N output current level is set by an external
resistor tied between REXT and GND. This output
current is determined by the following equation where R is
the value of REXT:
I
out
= (R/10K) * I
ref
Where I
ref
= 40 mA (100 Mbps, UTP)
= 32.6 mA (100 Mbps, STP)
= 100 mA (10 Mbps, UTP)
= 81.6 mA (10 Mbps, STP)
For 100 Ohm UTP REXT should be typically set to 10K
ohms and REXT should be a 1% resistor in order to meet
IEEE 802.3 specified levels. Once REXT is set for the
100 Mbps and UTP modes as shown by the equation
above, I
ref
is then automatically changed inside the
device when the 10 Mbps mode or UTP120/STP150
modes are selected as described in the TWISTED PAIR
CHARACTERISTICS TRANSMIT Section.
Keep resistor REXT as close to pins REXT and GND as
possible in order to reduce noise pickup into the
transmitter.
Since the TP output is a current source, capacitive and
inductive loading can reduce the output voltage level from
the ideal. Thus, in an actual application, it might be
necessary to adjust the value of the output current to
compensate for external loading. One way to adjust the
TP output level is to change the value of the external
resistor tied to REXT A better way to adjust the TP
output level is to use the transmit level adjust register bits
accessed through the MI serial port. These four bits can
adjust the output level by -14% to +16% in 2% steps as
Vendor
Pulse
bel
Part Number
H1062
S558-
5999B47
6931-30
ST6179
TG110-
S453NX
H1053
Pin Out Type
Stacked
Stacked
nano pulse
Valor
Halo
Stacked
Stacked
Stacked
Pulse
Non-
Stacked
Non-
Stacked
Non -
Stacked
Non-
Stacked
Non-
Stacked
bel
S558-5999-
J5
6949-30
nano pulse
Valor
ST6403P
Halo
TG110-
S456NX
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 84221 | 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99 |
| 84221 | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 84301 | 84301 4-Port Fast Ethernet Controller manual 3/98 |
| 84301 | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 84717000 | MINIATURNAEHERUNGSSCHALTER 4MM GLATT PNP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 8422002AGI | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI - Rail/Tube |
| 8422002AGI-01 | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01 - Rail/Tube |
| 8422002AGI-01LF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER |
| 8422002AGI-01LFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER |
| 8422002AGI-01T | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01T - Tape and Reel |
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