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參數(shù)資料
| 型號： | 84220 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ） |
| 文件頁數(shù)： | 56/92頁 |
| 文件大小： | 1401K |
| 代理商： | 84220 |
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MD400177/B
84220
4.10.4 Serial Port Addressing
The device address for the MI serial port is selected by
connecting the PHYAD[4:2] pins to the desired value. The
PHYAD[1:0] addresses are internally hardwired for each
channel as shown in both Tables 7 and 9.
4.11 UNMANAGED PORT CONFIGURATION
The 84220 has configuration inputs which can “over-ride”
the default configuration state obtained on POWER-UP or
RESET of the device. Use of these pins ANEG,
SPEED_[3:0], and DPLX_[3:0] allow selection of Global
Autonegotiation, Individual Port Speed (10/100), and
Individual Port Duplex (Full/Half), by properly strapping
these pins to VDD or VSS as shown in Table 27. Note
that these pins SHOULD NOT FLOAT but must be
connected either High or Low for proper operation
In order to obtain the “Default Mode of Operation”, ie:
Auto-negotiation enabled, 100MBs, and Half Duplex; the
ANEG, SPEED_[3:0], and DPLX_[3:0] pins should be set
to 1,1,0 respectively.
Note that if the Repeater mode is activated by asserting
the Repeater pin, these Hardware configuration pins will
have no effect.
Table 27. Hardware Configuration
4.13 LONG CABLE
IEEE 802.3 specifies that 10BaseT and 100BaseTX
operate over twisted pair cable lengths from 0 to 100
meters. The squelch levels can be reduced by 4.5 dB if
the receive level adjust bit is appropriately set in the MI
serial port Channel Configuration register, which will allow
the 84220 to operate with up to 150 meters of twisted pair
cable. The equalizer is already designed to accomodate
between 0 to 150 meters of cable.
4.14 AUTOMATIC JAM
The 84220 has an automatic JAM generation feature
which automatically transmits a JAM packet when receive
activity is detected. This feature is primarily designed to
give the user a means to easily implement half duplex
flow control. In a typical application, a watermark signal
from a system FIFO can be tied directly to the JAM pin.
Thus, when the system FIFO is nearly full and more data
is incoming, the device will automatically transmit a JAM
packet and create a collision which will cause the far end
device to backoff allowing time for the system FIFO to
empty itself.
4.15 CLOCK
The 84220 requires a 25 MHz reference frequency for
internal signal generation in MII mode, and 50 MHz in
RMII mode. The appropriate reference frequency must
be applied to the CLKIN pin.
4.16 LED DRIVERS
The LED[3:0] outputs can all drive LED’s tied to VDD as
shown in Figure 12 and Figure 13. In addition, the
LED[3:0] outputs can drive LED’s tied to GND as well.
The LED definitions assume that the LED outputs are tied
to VDD, active low signals (otherwise the LED outputs will
indicate their respective opposite events.)
The LED[3:0] outputs can be programmed to indicate
eight specific sets of events, by appropriately setting the
LED definition bits in the MI serial port Global
Configuration register. The LED DRIVERS Section
describes the programmable LED definition bit settings.
The LEDDEF pin determines the default settings for
LED[3:0]. If LEDDEF = 0, the default functions for
LED[3:0] are Link 100, Activity, Full Duplex, and Link 10,
respectively. If LEDDEF = 1, the LED functions for
LED[3:0] are forced to LINK + ACTIVITY Collision, Full
Duplex and 10/100 Mbps operation, respectively. Table 5
defines the LED functions. Table 6 defines the LED
events.
The LED[3:0] outputs can also drive other digital inputs.
Thus, LED[3:0] can also be used as digital outputs whose
function can be user defined and controlled through the
MI serial port.5V Compatible I/O Operation.
Configuration
State
Auto-
Negotiate
Speed
Duplex
Normal
(POC/RESET)
Config Pins
Enabled
100MBs
Half
ANEG=1
SPEED_
[3:0]=1
10MBs
DPLX_
[3:0]=0
Full
Complement
State
Config Pins
Disabled
ANEG=0
SPEED_
[3:0]=0
DPLX_
[3:0]=1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 84221 | 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99 |
| 84221 | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）) |
| 84301 | 84301 4-Port Fast Ethernet Controller manual 3/98 |
| 84301 | 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器) |
| 84717000 | MINIATURNAEHERUNGSSCHALTER 4MM GLATT PNP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 8422002AGI | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI - Rail/Tube |
| 8422002AGI-01 | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01 - Rail/Tube |
| 8422002AGI-01LF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER |
| 8422002AGI-01LFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER |
| 8422002AGI-01T | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01T - Tape and Reel |
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