參數(shù)資料
型號: 84220
廠商: LSI Corporation
英文描述: Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device (Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications)(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器(高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器))
中文描述: 四100BaseTX/100BaseFX/10BaseT物理層裝置(高度集成的以太網(wǎng)收發(fā)器,雙絞線和光纖以太網(wǎng)的應(yīng)用)(四通道100BaseTX/100BaseFX/10BaseT物理層處理器(高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器) )
文件頁數(shù): 7/92頁
文件大?。?/td> 1401K
代理商: 84220
MD400177/B
84220
7
1.0 PIN DESCRIPTION (cont’d)
LED
Pin #
Pin Name
I/O
Description
117
116
115
114
LED3_[3:0]
O
LED Output.
outputs assuming LEDDEF = 0. These pins can also be programmed
through the MI serial port to indicate other events. These pins can drive an
LED from both VDD and GND.
The default functions of these pins are 100 Mbps Link Detect
When programmed as 100 Mbps Link Detect Output:
1 = No Detect
0 = 100 Mbps Link Detected
3
6
10
13
LED2_[3:0]
O
LED Output.
assuming LEDDEF = 0. These pins can also be programmed through the MI
serial port to indicate other events. These pins can drive an LED from both
VDD and GND.
The default functions of these pins are Activity Detect outputs
When programmed as Activity Detect Output:
1 = No Activity
0 = Transmit or Receive Packet Occurred, Hold Low For 100 mS
2
5
9
12
LED1_[3:0]
O
LED Output.
outputs assuming LEDDEF = 0. These pins can also be programmed
through the MI serial port to indicate other events. These pins can drive an
LED from both VDD and GND.
The default functions of these pins are Full Duplex Detect
When programmed as Full Duplex Detect Output:
1 = Half Duplex
0 = Full Duplex
1
4
8
11
LED0_[3:0]
O
LED Output.
outputs assuming LEDDEF = 0. These pins can also be programmed
through the MI serial port to indicate other events. These pins can drive an
LED from both VDD and GND.
The default functions of these pins are 10 Mbps Link Detect
When programmed as 10 Mbps Link Detect Output:
1 = No Detect
0 = 10 Mbps Link Detected
110
LEDDEF
I
LED Default Select Input.
LED’s in the MI Serial Port Global Configuration Register.
This pin changes the default selection for the
1 = Bits 16.[13:11] Forced to 001
(LINK + ACT, COL, FDX, 10/100)
0 = Bits 16.[13:11] Default to 000
(LINK100, ACT, FDX, LNK10)
Drivers
相關(guān)PDF資料
PDF描述
84221 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99
84221 Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device (Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications)(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器(高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器))
84301 84301 4-Port Fast Ethernet Controller manual 3/98
84301 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
84717000 MINIATURNAEHERUNGSSCHALTER 4MM GLATT PNP
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