- 您現在的位置：買賣IC網 > PDF目錄364515 > 84220 (LSI Corporation) Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網雙絞線和光纖數據收發(fā)器）) PDF資料下載
參數資料
| 型號： | 84220 |
| 廠商： | LSI Corporation |
| 英文描述： | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網雙絞線和光纖數據收發(fā)器）) |
| 中文描述： | 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網收發(fā)器，雙絞線和光纖以太網的應用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網雙絞線和光纖數據收發(fā)器） ） |
| 文件頁數： | 5/92頁 |
| 文件大?。?/td> | 1401K |
| 代理商： | 84220 |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
MD400177/B
84220
5
1.0 PIN DESCRIPTION (cont’d)
Controller Interface (MII & RMII)
Pin #
Pin Name
I/O
Description
87
69
50
31
TXCLK_[3:0]
O
Transmit Clock Output.
controllers. Transmit data from the controller on TXD, TXEN, and TXER is
clocked in on the rising edges of TXCLK and CLKIN.
These interface outputs provide clocks to external
88
70
51
32
TXEN_[3:0]
I
Transmit Enable Input.
high to allow data on TXD and TXER to be clocked in on the rising edges of
TXCLK and CLKIN.
These interface inputs must be be asserted active
[92:89]
[74:71]
[55:52]
[36:33]
TXD[3:0]_3
TXD[3:0]_2
TXD[3:0]_1
TXD[3:0]_0
I
Transmit Data Input.
transmitted on the TP or FX outputs and are clocked in on rising edges of
TXCLK and CLKIN. In RMII mode, only TXD[1:0] are used.
These interface inputs contain input nibble data to be
86
68
49
30
TXER_[3:0]/
TXD4_[3:0]
I
Transmit Error Input.
transmitted on the TP or FX outputs and are clocked in on rising edges of
TXCLK when TXEN is asserted.
These interface inputs initiate an error pattern to be
If the channel is placed in the Bypass 4B5B Encoder mode, these pins are
reconfigured to be the fifth TXD transmit data input, TXD4. In RMII mode,
these pins are not used.
84
66
47
28
RXCLK_[3:0]
O
Receive Clock Output.
controller. Receive data on RXD, RXDV, and RXER is clocked out to the
controller on falling edges of RXCLK.
These interface outputs provide a clock to the
94
76
58
38
CRS_[3:0]
O
Carrier Sense Output.
when valid data is detected on the receive TP or FX inputs and is clocked
out on the falling edge of RXCLK.
These interface outputs are asserted active high
83
65
46
27
RXDV_[3:0]
O
Receive Data Valid Output.
high when valid decoded data is present on the RXD outputs and is clocked
out on falling edges of RXCLK. In RMII mode, these pins are not used.
These interface outputs are asserted active
[79:82]
[61:64]
[42:45]
[23:26]
RXD[3:0]_3
RXD[3:0]_2
RXD[3:0]_1
RXD[3:0]_0
O
Receive Data Output.
data from the TP or FX inputs and are clocked out on the falling edges of
RXCLK. In RMII mode, only RXD[1:0] are used.
These interface outputs contain recovered nibble
85
67
48
29
RXER_[3:0]/
RXD4_[3:0]
O
Receive Error Output.
when coding or other specified errors are detected on the TP or FX inputs
and are clocked out on falling edges of RXCLK.
These interface outputs are asserted active high
If the channel is placed in the Bypass 4B5B Decoder mode, these pins are
reconfigured to be the fifth RXD receive data output, RXD4.
93
75
57
37
COL_[3:0]
O
Collision Output.
collision between transmit and receive data is detected.
These interface outputs are asserted active high when
相關PDF資料 |
PDF描述 |
|---|---|
| 84221 | 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99 |
| 84221 | Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網雙絞線和光纖數據收發(fā)器）) |
| 84301 | 84301 4-Port Fast Ethernet Controller manual 3/98 |
| 84301 | 4-Port Fast Ethernet Controller( 4端口快速以太網控制器) |
| 84717000 | MINIATURNAEHERUNGSSCHALTER 4MM GLATT PNP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 8422002AGI | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI - Rail/Tube |
| 8422002AGI-01 | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01 - Rail/Tube |
| 8422002AGI-01LF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER |
| 8422002AGI-01LFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TOLVHSTL FREQUENCY SYNTHESIZER |
| 8422002AGI-01T | 制造商:Integrated Device Technology Inc 功能描述:8422002AGI-01T - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。