參數(shù)資料
型號(hào)： 84220
廠商： LSI Corporation
英文描述： Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
中文描述： 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ）
文件頁(yè)數(shù)： 21/92頁(yè)
文件大?。?/td> 1401K
代理商： 84220
MD400177/B
84220
21
2.10 FIBER INTERFACE
2.10.1 General
The Fiber Interface implements the 100BaseFX function
defined in IEEE 802.3.
The Fiber Interface consists of three signals: (1) a
differential PECL data output (FXOP/FXON), (2) a
differential PECL data input (FXIP/FXIN), and (3) a PECL
signal detect (SD/FXEN).
The Fiber Interface section consists of four blocks: (1)
transmitter, (2) receiver, (3) signal detect, and (4) far end
fault.
The Fiber Interface can be independently selected for
each channel with the SD/FXEN_[3:0] pins.
The Fiber Interface is disabled in 10Mbps mode.
Autonegotiation and the scrambler/descrambler are
disabled when the Fiber Interface is enabled.
The Fiber Interface meets all IEEE 802.3 requirements.
2.10.2 Transmitter
The FX transmitter converts data from the 4B5B encoder
into binary NRZI data and outputs the data onto the
FXOP/FXON pins for each channel. The output driver is a
differential current source that will drive a 100 ohm load to
ECL levels. The FXOP/FXON pins can directly drive an
external fiber optic transceiver. The FX transmitter meets
all the requirements defined in IEEE 802.3.
The FX transmit output current level is derived from an
internal reference voltage and the external resistor on
REXT pin. The FX transmit level can be adjusted with this
resistor or it can also be adjusted with the two FX
transmit level adjust bits in the Configuration register as
shown in Table 4.
Table 4. FX Transmit Level Adjust
FLVL[1:0] Bits
11
10
01
00
Gain
1.30
1.15
1.00 (default)
0.85
2.10.3 Receiver
The FX receiver (1) converts the differential ECL inputs on
the FXIP/FXIN pins for each channel to a digital bit
stream, (2) validates the data on FXIP/FXIN with the SD/
FXEN input pin for each channel, and (3) enable/disables
the Fiber Interface with the SD/FXEN pin for each
channel. The FX receiver meets all requirements defined
in IEEE 802.3.
The input to the FXIP/FXIN pins can be directly driven
from a fiber optic transceiver and first goes to a
comparator. The comparator compares the input
waveform against the internal ECL threshold levels to
produce a low jitter serial bit stream with internal logic
levels. The data from the comparator output is then
passed to the clock and data recovery block provided the
signal detect input, SD/FXEN, is asserted. The signal
detect function is described in the next section.
2.10.4 Signal Detect
The FX receiver has a signal detect input pin, SD/FXEN,
for each channel which indicates whether the incoming
data on FXIP/FXIN is valid or not for that channel. The
SD/FXEN pin can be driven directly from an external fiber
optic transceiver and meets all requirements defined in
the IEEE 802.3 specifications.
The SD/FXEN input goes directly to a comparator. The
comparator compares the input waveform against the
internal ECL threshold level to produce a digital signal
with internal logic levels. The output of the signal detect
comparator then goes to the link integrity and squelch
blocks. If the signal detect input is asserted, the channel
is placed in the Link Pass state and the input data on
FXIP/FXIN is determined to be valid. If the signal detect
input is deasserted, the channel is placed in the Link Fail
state and the input data on FXIP/FXIN is determined to be
invalid.
The SD_THR pin adjusts the ECL trip point of the SD/
FXEN input. When the SD_THR pin is tied to a voltage
between GND and GND+0.45V the trip point of the SD
ECL input buffer is internally set to VCC-1.3V When
SD_THR pin is set to a voltage greater than GND+0.85v,
the trip point of the SD SD/FXEN ECL input buffer is set to
the voltage that is applied to the SD_THR pin. The trip
level for the SD/FXEN input buffer must be set to VCC-
1.3V Having external control of the SD/FXEN buffer trip
level with the SD_THR pin allows this trip level to be
referenced to an external supply which facilitates
connection to both 3.3V and 5V external fiber optic
transceiver. If the device is to be connected to a 3.3V
external fiber optic transceiver, then SD_THR should be
tied to GND. If the device is to be connected to a 5V
external fiber optic transceiver, then SD_THR needs to be
tied to VCC-1.3V and this can be done so with an external
resistor divider. Refer to the Applications section for more
details on connections to external fiber optic transceivers.
相關(guān)PDF資料
PDF描述
84221 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99
84221 Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
84301 84301 4-Port Fast Ethernet Controller manual 3/98
84301 4-Port Fast Ethernet Controller( 4端口快速以太網(wǎng)控制器)
84717000 MINIATURNAEHERUNGSSCHALTER 4MM GLATT PNP
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