
30
MD400177/B
84220
Table 5.  LED Function Definition
Notes:
When the FX interface is enabled, LED0 becomes FEF.
Default = 000 When pin LEDDEF = 0
Bits 16. [13:11] forced to 001 When 
     pin LEDDEF = 1
Table 6.  LED Event Definition
2.25  REPEATER MODE
The 84220 has one predefined repeater mode which can
be enabled by either asserting the REPEATER pin or by
setting the repeater mode bit in the Global Configuration
register.  When this mode is enabled the device operation
is altered as follows:
 TXEN to CRS loopback is disabled.
 AutoNegotiation is disabled.
 100 Mbps operation is enabled.
 Half Duplex operation is enabled.
Bits 
16.[13:11]
111
LED3
LINK +
ACT
LINK
LINK
LINK
LINK
LINK
LINK +
ACT
LINK
100
LED2
COL
LED1
10/100
LED0
FDX
110
101
100
011
010
001
RXACT
RXACT
RXACT
COL
ACT
COL
TXACT
TXACT
TXACT
FDX
FDX
FDX
COL
FDX
10/100
10/100
10/100
10/100
000
ACT
FDX
LINK10
Symbol
ACT
Definition
Activity Occurred, Stretch Pulse to 
100 mS
Collision Occurred, Stretch Pulse to 
100 mS
100 Mb Link Detected
10 Mb Link Detected
100 Mb or 10 Mb Link Detected
LED on if Link Detected (10 or 100).
LED Blinks if Activity Determined, 
Stretch Pulse to 100 mS
Full Duplex Mode Enabled
10 Mb Mode Enabled (High) or
100 Mb Mode Enabled (Low)
COL
LINK100
LINK10
LINK
LINK+ACT
FDX
10/100
Note that the repeater mode, enabled by the REPEATER
pin, is only one of many possible repeater modes
available on the device  Other modes are available by
setting the appropriate register bits or pins to enable or
disable the desired functions for a given repeater mode
type. For detailed information on other possible repeater
modes, refer to the REPEATER APPLICATIONS Section.
2.26  MI SERIAL PORT
2.26.1  Signal Description
The MI serial port has six pins, MDC, MDIO, MDINT and
PHYAD[4:2]. MDC is the serial shift clock input. MDIO is a
bidirectional data I/O pin. MDINT is an interrupt output.
PHYAD[4:2] are physical address pins.
Pins PHYAD[4:2] set the three most significant bits of the
PHY address. The two least significant bits of the PHY
address are set internally to match the channel number,
as shown in Table 7.
Table 7.  PHYAD[1:0] Settings
2.26.2 Timing
Figure 10 shows a timing diagram for a MI serial port
cycle.
The MI serial port is idle when at least 32 continuous 1's
are detected on MDIO and remains idle as long as
continuous 1's are detected. During idle, MDIO is in the
high impedance state. When the MI serial port is in the
idle state, a 01 pattern on the MDIO pin initiates a serial
shift cycle. Data on MDIO is then shifted in on the next 14
rising edges of MDC (MDIO is high impedance). If the
register access mode is not enabled, on the next 16 rising
edges of MDC, data is either shifted in or out on MDIO,
depending on whether a write or read cycle was selected
with the bits READ and WRITE. After the 32 MDC cycles
have been completed, one complete register has been
read/written, the serial shift process is halted, data is
latched into the device, and MDIO goes into high
impedance state. Another serial shift cycle cannot be
initiated until the idle condition (at least 32 continuous 1's)
is detected.
PHYAD1
1
 PHYAD0
1
Channel 3
Channel 2
1
0
Channel 1
0
1
Channel 0
0
0