參數(shù)資料
型號(hào)： 84220
廠商： LSI Corporation
英文描述： Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
中文描述： 四100BaseTX/100BaseFX/10BaseT物理層裝置（高度集成的以太網(wǎng)收發(fā)器，雙絞線和光纖以太網(wǎng)的應(yīng)用）（四通道100BaseTX/100BaseFX/10BaseT物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器） ）
文件頁(yè)數(shù)： 33/92頁(yè)
文件大?。?/td> 1401K
代理商： 84220
MD400177/B
84220
33
(2) INT bit in the Channel Status Output Register
The INT bit is an active high interrupt register bit that
resides in the Channel Status Output Register.
(3) Interrupt pulse on MDIO.
The interrupt pulse on MDIO also indicates interrupt
and is available when the interrupt scheme select bit
is set in the Global Configuration Register. When this
bit is set, an interrupt is signaled by a low going pulse
on MDIO when MDC is high and the serial port is in
the idle state, as shown in the timing diagram in
Figure 10. After this low pulse MDIO goes back to
high impedance state. If the interrupt occurs while the
serial port is being accessed, then the MDIO interrupt
pulse is delayed until one clock bit after the serial port
access cycle is ended as shown in Figure 11.
2.26.8 Interrupt Register Read
If the MDINT pin is asserted low (and INT bit(s) set high),
one or more of the interrupt bits from one or more
channels have changed since the last serial port read
operation.
A quick way to determine which channel contains the
interrupt is to do a Register Read with REGAD(4:0) set to
11110. The accessed information is not determined by
REGAD anymore. Instead, the data accessed is from the
Channel Status Output Register where the interrupt bit
has changed. The channel address of this Channel Status
Output Register can be found from the CHAD[1:0] bits in
this register.
After this “interrupted” register is read, the interrupt bit
(INT) for that channel is cleared. If more than one INT
register bits are set and Interrupt Register Read is used to
access them, the Channel Status Output Registers are
accessed in numerical order from 0 to 3 on each read
cycle. After all INT bits have been cleared in all Channel
Status Output registers, the MDINT pin is deasserted.
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84221 84221 Quad 10/100 Mbps TX/FX/10BT (PHY) manual 1/99
84221 Quad 100BaseTX/100BaseFX/10BaseT Physical Layer Device （Highly Integrated Ethernet Transceiver For Twisted Pair And Fiber Ethernet Applications）(四通道100BaseTX/100BaseFX/10BaseT 物理層處理器（高度集成的以太網(wǎng)雙絞線和光纖數(shù)據(jù)收發(fā)器）)
84301 84301 4-Port Fast Ethernet Controller manual 3/98
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